CH3_INTCLEARREG 

         Writing 1 to specific field will clear the corresponding field in Channelx Interrupt Status Register(CHx_IntStatusReg).
Module Instance Base Address Register Address
i_dma__dmac1_ahb_slv__10dc0000__Channel3_Registers_Address_Block__SEG_L4_AHB_dmac1_s_0x0_0x10000 0x10DC0300 0x10DC0398

Size: 64

Offset: 0x98

Access: WO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RSVD_DMAC_CHx_INTCLEARREG_36to63

WO 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD_DMAC_CHx_INTCLEARREG_36to63

WO 0x0

Clear_ECC_PROT_UIDMem_UnCorrERR_IntStat

WO 0x0

Clear_ECC_PROT_UIDMem_CorrERR_IntStat

WO 0x0

Clear_ECC_PROT_CHMem_UnCorrERR_IntStat

WO 0x0

Clear_ECC_PROT_CHMem_CorrERR_IntStat

WO 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Clear_CH_ABORTED_IntStat

WO 0x0

Clear_CH_DISABLED_IntStat

WO 0x0

Clear_CH_SUSPENDED_IntStat

WO 0x0

Clear_CH_SRC_SUSPENDED_IntStat

WO 0x0

Clear_CH_LOCK_CLEARED_IntStat

WO 0x0

RSVD_DMAC_CHx_INTCLEARREG_26

WO 0x0

Clear_SLVIF_WRPARITY_ERR_IntStat

WO 0x0

RSVD_DMAC_CHx_INTCLEARREG_22to24

WO 0x0

Clear_SLVIF_WRONHOLD_ERR_IntStat

WO 0x0

Clear_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat

WO 0x0

Clear_SLVIF_WRONCHEN_ERR_IntStat

WO 0x0

Clear_SLVIF_RD2RWO_ERR_IntStat

WO 0x0

Clear_SLVIF_WR2RO_ERR_IntStat

WO 0x0

Clear_SLVIF_DEC_ERR_IntStat

WO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_DMAC_CHx_INTCLEARREG_15

WO 0x0

Clear_SLVIF_MULTIBLKTYPE_ERR_IntStat

WO 0x0

Clear_SHADOWREG_OR_LLI_INVALID_ERR_IntStat

WO 0x0

Clear_LLI_WR_SLV_ERR_IntStat

WO 0x0

Clear_LLI_RD_SLV_ERR_IntStat

WO 0x0

Clear_LLI_WR_DEC_ERR_IntStat

WO 0x0

Clear_LLI_RD_DEC_ERR_IntStat

WO 0x0

Clear_DST_SLV_ERR_IntStat

WO 0x0

Clear_SRC_SLV_ERR_IntStat

WO 0x0

Clear_DST_DEC_ERR_IntStat

WO 0x0

Clear_SRC_DEC_ERR_IntStat

WO 0x0

Clear_DST_TRANSCOMP_IntStat

WO 0x0

Clear_SRC_TRANSCOMP_IntStat

WO 0x0

RSVD_DMAC_CHx_INTCLEARREG_2

WO 0x0

Clear_DMA_TFR_DONE_IntStat

WO 0x0

Clear_BLOCK_TFR_DONE_IntStat

WO 0x0

CH3_INTCLEARREG Fields

Bit Name Description Access Reset
63:36 RSVD_DMAC_CHx_INTCLEARREG_36to63 
DMAC Channelx Interrupt Clear Register (bits 36to63) Reserved bit - Read Only
 WO 0x0
35 Clear_ECC_PROT_UIDMem_UnCorrERR_IntStat 
ECC Protection Uncorrectable UID Memory Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the ECC_PROT_UIDMem_UnCorrERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
34 Clear_ECC_PROT_UIDMem_CorrERR_IntStat 
ECC Protection Correctable UID Memory Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the ECC_PROT_UIDMem_CorrERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
33 Clear_ECC_PROT_CHMem_UnCorrERR_IntStat 
ECC Protection Uncorrectable Channel Memory Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the ECC_PROT_CHMem_UnCorrERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
32 Clear_ECC_PROT_CHMem_CorrERR_IntStat 
ECC Protection Correctable Channel Memory Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the ECC_PROT_CHMem_CorrERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
31 Clear_CH_ABORTED_IntStat 
Channel Aborted Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the CH_ABORTED interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
30 Clear_CH_DISABLED_IntStat 
Channel Disabled Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the CH_DISABLED interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
29 Clear_CH_SUSPENDED_IntStat 
Channel Suspended Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the CH_SUSPENDED interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
28 Clear_CH_SRC_SUSPENDED_IntStat 
Channel Source Suspended Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the CH_SRC_SUSPENDED interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
27 Clear_CH_LOCK_CLEARED_IntStat 
Channel Lock Cleared Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the CH_LOCK_CLEARED interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
26 RSVD_DMAC_CHx_INTCLEARREG_26 
DMAC Channelx Interrupt Clear Register (bit 26) Reserved bit - Read Only
 WO 0x0
25 Clear_SLVIF_WRPARITY_ERR_IntStat 
Slave Interface Write Parity Error Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the SLVIF_WRPARITY_ERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
24:22 RSVD_DMAC_CHx_INTCLEARREG_22to24 
DMAC Channelx Interrupt Clear Register (bits 22to24) Reserved bit - Read Only
 WO 0x0
21 Clear_SLVIF_WRONHOLD_ERR_IntStat 
Slave Interface Write On Hold Error Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in
CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the SLVIF_WRONHOLD_ERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
20 Clear_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat 
Shadow Register Write On Valid Error Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in
CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the SLVIF_SHADOWREG_WRON_VALID_ERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
19 Clear_SLVIF_WRONCHEN_ERR_IntStat 
Slave Interface Write On Channel Enabled Error Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in
CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the SLVIF_WRONCHEN_ERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
18 Clear_SLVIF_RD2RWO_ERR_IntStat 
Slave Interface Read to write Only Error Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in
CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the SLVIF_RD2RWO_ERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
17 Clear_SLVIF_WR2RO_ERR_IntStat 
Slave Interface Write to Read Only Error Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in
CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the SLVIF_WR2RO_ERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
16 Clear_SLVIF_DEC_ERR_IntStat 
Slave Interface Decode Error Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in
CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the SLVIF_DEC_ERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
15 RSVD_DMAC_CHx_INTCLEARREG_15 
DMAC Channelx Interrupt Clear Register (bit 15) Reserved bit - Read Only
 WO 0x0
14 Clear_SLVIF_MULTIBLKTYPE_ERR_IntStat 
Slave Interface Multi Block type Error Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in
CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the SLVIF_MULTIBLKTYPE_ERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
13 Clear_SHADOWREG_OR_LLI_INVALID_ERR_IntStat 
Shadow register or LLI Invalid Error Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in
CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the SHADOWREG_OR_LLI_INVALID_ERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
12 Clear_LLI_WR_SLV_ERR_IntStat 
LLI WRITE Slave Error Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the LLI_WR_SLV_ERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
11 Clear_LLI_RD_SLV_ERR_IntStat 
LLI Read Slave Error Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the LLI_RD_SLV_ERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
10 Clear_LLI_WR_DEC_ERR_IntStat 
LLI WRITE Decode Error Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the LLI_WR_DEC_ERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
9 Clear_LLI_RD_DEC_ERR_IntStat 
LLI Read Decode Error Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the LLI_RD_DEC_ERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
8 Clear_DST_SLV_ERR_IntStat 
Destination Slave Error Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the DST_SLV_ERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
7 Clear_SRC_SLV_ERR_IntStat 
Source Slave Error Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the SRC_SLV_ERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
6 Clear_DST_DEC_ERR_IntStat 
Destination Decode Error Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the DST_DEC_ERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
5 Clear_SRC_DEC_ERR_IntStat 
Source Decode Error Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the SRC_DEC_ERR interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
4 Clear_DST_TRANSCOMP_IntStat 
Destination Transaction Completed Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in
CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the DST_TRANSCOMP interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
3 Clear_SRC_TRANSCOMP_IntStat 
Source Transaction Completed Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in
CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the SRC_TRANSCOMP interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
2 RSVD_DMAC_CHx_INTCLEARREG_2 
DMAC Channelx Interrupt Clear Register (bit 2) Reserved bit - Read Only
 WO 0x0
1 Clear_DMA_TFR_DONE_IntStat 
DMA Transfer Done Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in
CHx_INTSTATUSREG.
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the DMA_TFR_DONE interrupt in the Interrupt Status Register(CH3_IntStatusReg).
WO 0x0
0 Clear_BLOCK_TFR_DONE_IntStat 
Block Transfer Done Interrupt Clear Bit.
This bit is used to clear the corresponding channel interrupt status bit in CH3_INTSTATUSREG
Value Description
0x0 Inactive signal. No action taken.
0x1 Clear the interrupt in the Interrupt Status Register(CHx_IntStatusReg). Writing a 1 to this register field clears the corresponding bit in the CHx_IntStatusReg register.
WO 0x0