CH3_CFG2 

         This register contains fields that configure the DMA transfer. This register should be programmed prior to enabling the channel.
Bits [63:32] of the
channel configuration register remains fixed for all blocks of a multi-block transfer and can be programmed only when channel is disabled.
Bits [3:0] of the channel configuration register can be
programmed even when channel is enabled.
Software clears these bits to end the multi-block transfers. For Contiguous-Address and Auto-Reloading-based multi-block transfers (if neither source nor destination peripheral uses Shadow-Register or Linked-List-based multi-block transfers), if the corresponding multi-block type selection bits namely CHx_CFG.SRC_MLTBLK_TYPE and/or CHx_CFG.DST_MLTBLK_TYPE bits are seen to be 2'b00 at the end of a block transfer, the DW_axi_dmac understands that the previous block was the final block in the transfer and completes the DMA transfer operation.
Module Instance Base Address Register Address
i_dma__dmac1_ahb_slv__10dc0000__Channel3_Registers_Address_Block__SEG_L4_AHB_dmac1_s_0x0_0x10000 0x10DC0300 0x10DC0320

Size: 64

Offset: 0x20

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RSVD_DMAC_CHx_CFG_63

RO 0x0

DST_OSR_LMT

RW 0x0

SRC_OSR_LMT

RW 0x0

LOCK_CH_L

RW 0x0

LOCK_CH

RW 0x0

CH_PRIOR

RW 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

CH_PRIOR

RW 0x0

RSVD_DMAC_CHx_CFG_39to46

RO 0x0

DST_HWHS_POL

RO 0x0

SRC_HWHS_POL

RO 0x0

HS_SEL_DST

RW 0x0

HS_SEL_SRC

RW 0x0

TT_FC

RW 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_DMAC_CHx_CFG_29to31

RO 0x0

WR_UID

RW 0x0

RSVD_DMAC_CHx_CFG_22to24

RO 0x0

RD_UID

RO 0x0

RSVD_DMAC_CHx_CFG_17

RO 0x0

DST_PER

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DST_PER

RW 0x0

RSVD_DMAC_CHx_CFG_10

RO 0x0

SRC_PER

RW 0x0

DST_MULTBLK_TYPE

RO 0x0

SRC_MULTBLK_TYPE

RO 0x0

CH3_CFG2 Fields

Bit Name Description Access Reset
63 RSVD_DMAC_CHx_CFG_63 
DMAC Channelx Transfer Configuration Register (63bit) Reserved bit - Read Only
 RO 0x0
62:59 DST_OSR_LMT 
Destination Outstanding Request Limit
 - Maximum outstanding request supported is 16.
 - Source Outstanding Request Limit = DST_OSR_LMT + 1
 RW 0x0
58:55 SRC_OSR_LMT 
Source Outstanding Request Limit
 - Maximum outstanding request supported is 16.
 - Source Outstanding Request Limit = SRC_OSR_LMT + 1
 RW 0x0
54:53 LOCK_CH_L 
Channel Lock Level
This bit indicates the duration over which CHx_CFG.LOCK_CH bit applies.
 - 00: Over complete DMA transfer
 - 01: Over DMA block transfer
 - 1x: Reserved
This field does not exist if the configuration parameter DMAX_CHx_LOCK_EN is set to False; in that case, the read-back value is always 0.
Value Description
0x0 Duration of the Channel locking is for the entire DMA transfer
0x1 Duration of the Channel locking is for the current block transfer
RW 0x0
52 LOCK_CH 
Channel Lock bit
When the channel is granted control of the master bus interface and if the CHx_CFG.LOCK_CH bit is asserted, then no other
channels are granted control of the master bus interface for the duration specified in CHx_CFG.LOCK_CH_L. Indicates to the master bus interface arbiter that this channel wants exclusive access to
the master bus interface for the duration specified in CHx_CFG.LOCK_CH_L.
This field does not exist if the configuration parameter DMAX_CHx_LOCK_EN is set to False; in this case, the
read-back value is always 0.
Locking the channel locks AXI Read Address, Write Address and Write Data channels on the corresponding master interface.
Note: Channel locking feature is
supported only for memory-to-memory transfer at Block Transfer and DMA Transfer levels. Hardware does not check for the validity of channel locking setting, hence the software must take care of
enabling the channel locking only for memory-to-memory transfers at Block Transfer or DMA Transfer levels. Illegal programming of channel locking might result in unpredictable behavior.
Value Description
0x0 Channel is locked and granted exclusive access to the Master Bus Interface
0x0 Channel is not locked during the transfers
RW 0x0
51:47 CH_PRIOR 
Channel Priority
A priority of DMAX_NUM_CHANNELS-1 is the highest priority, and 0 is the lowest. This field must be programmed within the following range:

     0: DMAX_NUM_CHANNELS-1
A programmed value outside this range will cause erroneous behavior.
 RW 0x0
46:39 RSVD_DMAC_CHx_CFG_39to46 
DMAC Channelx Transfer Configuration Register (bits 39to46) Reserved bits - Read Only
 RO 0x0
38 DST_HWHS_POL 
Destination Hardware Handshaking Interface Polarity.
 - 0: ACTIVE HIGH
 - 1: ACTIVE LOW
Value Description
0x0 Polarity of the Handshaking Interface used for the Destination peripheral is Active High
0x1 Polarity of the Handshaking Interface used for the Destination peripheral is Active Low
RO 0x0
37 SRC_HWHS_POL 
Source Hardware Handshaking Interface Polarity.
 - 0: ACTIVE HIGH
 - 1: ACTIVE LOW
Value Description
0x0 Polarity of the Handshaking Interface used for the Source peripheral is Active High
0x1 Polarity of the Handshaking Interface used for the Source peripheral is Active Low
RO 0x0
36 HS_SEL_DST 
Destination Software or Hardware Handshaking Select.
This register selects which of the handshaking interfaces (hardware or software) is active for destination requests on this channel.
 - 0: Hardware handshaking interface. Software-initiated transaction requests are ignored.
 - 1: Software handshaking interface. Hardware-initiated transaction requests are ignored.
If the destination peripheral is memory, then this bit is ignored.
Value Description
0x0 Hardware Handshaking Interface is used for the Destination peripheral
0x1 Software Handshaking Interface is used for the Destination peripheral
RW 0x0
35 HS_SEL_SRC 
Source Software or Hardware Handshaking Select.
This register selects which of the handshaking interfaces (hardware or software) is active for source requests on this channel.
 - 0: Hardware handshaking interface. Software-initiated transaction requests are ignored.
 - 1: Software handshaking interface. Hardware-initiated transaction requests are ignored.
If the source peripheral is memory, then this bit is ignored.
Value Description
0x0 Hardware Handshaking Interface is used for the Source peripheral
0x1 Software Handshaking Interface is used for the Source peripheral
RW 0x0
34:32 TT_FC 
Transfer Type and Flow Control.
The following transfer types are supported.
 - Memory to Memory 
 - Memory to Peripheral 
 - Peripheral to Memory 
 - Peripheral to Peripheral 
 Flow Control can be assigned to the DW_axi_dmac, the source peripheral, or hte destination peripheral.
Value Description
0x0 Transfer Type is memory to memory and Flow Controller is DW_axi_dmac
0x1 Transfer Type is memory to peripheral and Flow Controller is DW_axi_dmac
0x2 Transfer Type is peripheral to memory and Flow Controller is DW_axi_dmac
0x3 Transfer Type is peripheral to peripheral and Flow Controller is DW_axi_dmac
0x4 Transfer Type is peripheral to Memory and Flow Controller is Source peripheral
0x5 Transfer Type is peripheral to peripheral and Flow Controller is Source peripheral
0x6 Transfer Type is memory to peripheral and Flow Controller is Destination peripheral
0x7 Transfer Type is peripheral to peripheral and Flow Controller is Destination peripheral
RW 0x0
31:29 RSVD_DMAC_CHx_CFG_29to31 
DMAC Channelx Transfer Configuration Register (bits 29to31) Reserved bits - Read Only
 RO 0x0
28:25 WR_UID 
Defines the number of AXI Unique ID's supported for the AXI Write Channel. The value programmed must be less than or equal to DMAX_CH(x)_WR_UID. Otherwise, it is limited by the value DMAX_CH(x)_WR_UID.
 RW 0x0
24:22 RSVD_DMAC_CHx_CFG_22to24 
DMAC Channelx Transfer Configuration Register (bits 22to24) Reserved bits - Read Only
 RO 0x0
21:18 RD_UID 
Defines the number of AXI Unique ID's supported for the AXI Read Channel. The value programmed must be less than or equal to DMAX_CH(x)_RD_UID. Otherwise, it is limited by the value DMAX_CH(x)_RD_UID.
 RO 0x0
17 RSVD_DMAC_CHx_CFG_17 
DMAC Channelx Transfer Configuration Register (bit 17) Reserved bit - Read Only
 RO 0x0
16:11 DST_PER 
Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the destination of Channelx if the CHx_CFG.HS_SEL_DST field is 0;
otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface.
Note: For correct DW_axi_dmac operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. 
This field does not exist if the configuration
parameter DMAX_NUM_HS_IF is set to 0.
x = 11 if DMAC_NUM_HS_IF is 1
x = ceil(log2(DMAC_NUM_HS_IF)) + 10 if DMAC_NUM_HS_IF is greater than 1
Bits 16: (x+1) do not exist and return 0 on a read.
 RW 0x0
10 RSVD_DMAC_CHx_CFG_10 
DMAC Channelx Transfer Configuration Register (bit 10) Reserved bit - Read Only
 RO 0x0
9:4 SRC_PER 
Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the source of Channelx if the CHx_CFG.HS_SEL_SRC field is 0; otherwise,
this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface.
Note: For correct DW_axi_dmac operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
This field does not exist if the configuration
parameter DMAX_NUM_HS_IF is set to 0.
x = 4 if DMAC_NUM_HS_IF is 1
x = ceil(log2(DMAC_NUM_HS_IF) + 3 if DMAC_NUM_HS_IF is greater than 1.
Bits 9: (x+1) do not exist and return 0 on a read.
 RW 0x0
3:2 DST_MULTBLK_TYPE 
Destination Multi Block Transfer Type.
These bits define the type of multi-block transfer used for destination peripheral.
 - 00: Contiguous
 - 01: Reload
 - 10: Shadow Register
 - 11: Linked List
If the type selected is Contiguous, the CHx_DAR register is loaded with the value of the end source address of previous block + 1 at the end of every block for multi-block transfers. A new block
transfer is then initiated.
If the type selected is Reload, the CHx_DAR register is reloaded from the initial value of DAR at the end of every block for multi-block transfers. A new block
transfer is then initiated.
If the type selected is Shadow Register, the CHx_DAR register is loaded from the content of its shadow register if CHx_CTL.ShadowReg_Or_LLI_Valid bit is set to 1
at the end of every block for multi-block transfers. A new block transfer is then initiated.
If the type selected is Linked List, the CHx_DAR register is loaded from the Linked List if
CTL.ShadowReg_Or_LLI_Valid bit is set to 1 at the end of every block for multi-block transfers. A new block transfer is then initiated.
CHx_CTL and CHx_BLOCK_TS registers are loaded from
their initial values or from the contents of their shadow registers (if CHx_CTL.ShadowReg_Or_LLI_Valid bit is set to 1) or from the linked list (if CTL.ShadowReg_Or_LLI_Valid bit is set to 1) at
the end of every block for multi-block transfers based on the multi-block transfer type programmed for source and destination peripherals.
Contiguous transfer on both source and destination
peripheral is not a valid multi-block transfer configuration.
This field does not exist if the configuration parameter DMAX_CHx_MULTI_BLK_EN is not selected; in that case, the read-back value is always 0.
Value Description
0x0 Contiguous Multiblock Type used for Destination Transfer
0x1 Reload Multiblock Type used for Destination Transfer
0x2 Shadow Register based Multiblock Type used for Destination Transfer
0x3 Linked List based Multiblock Type used for Destination Transfer
RO 0x0
1:0 SRC_MULTBLK_TYPE 
Source Multi Block Transfer Type.
These bits define the type of multi-block transfer used for source peripheral.
 - 00: Contiguous
 - 01: Reload
 - 10: Shadow Register
 - 11: Linked List
If the type selected is Contiguous, the CHx_SAR register is loaded with the value of the end source address of previous block + 1 at the end of every block for multi-block transfers. A new block
transfer is then initiated.
If the type selected is Reload, the CHx_SAR register is reloaded from the initial value of SAR at the end of every block for multi-block transfers. A new block
transfer is then initiated.
If the type selected is Shadow Register, the CHx_SAR register is loaded from the content of its shadow register if CHx_CTL.ShadowReg_Or_LLI_Valid bit is set to 1
at the end of every block for multi-block transfers. A new block transfer is then initiated.
If the type selected is Linked List, the CHx_SAR register is loaded from the Linked List if
CTL.ShadowReg_Or_LLI_Valid bit is set to 1 at the end of every block for multi-block transfers. A new block transfer is then initiated.
CHx_CTL and CHx_BLOCK_TS registers are loaded from
their initial values or from the contents of their shadow registers (if CHx_CTL.ShadowReg_Or_LLI_Valid bit is set to 1) or from the linked list (if CTL.ShadowReg_Or_LLI_Valid bit is set to 1) at
the end of every block for multi-block transfers based on the multi-block transfer type programmed for source and destination peripherals.
Contiguous transfer on both source and destination
peripheral is not a valid multi-block transfer configuration.
This field does not exist if the configuration parameter DMAX_CHx_MULTI_BLK_EN is not selected; in that case, the read-back value is always 0.
Value Description
0x0 Contiguous Multiblock Type used for Source Transfer
0x1 Reload Multiblock Type used for Source Transfer
0x2 Shadow Register based Multiblock Type used for Source Transfer
0x3 Linked List based Multiblock Type used for Source Transfer
RO 0x0