CH3_AXI_QOSREG 

         Channelx AXI QOS Register. This register is allowed to be updated only when the channel is disabled, which means that it remains fixed for the entire
DMA transfer.
Module Instance Base Address Register Address
i_dma__dmac1_ahb_slv__10dc0000__Channel3_Registers_Address_Block__SEG_L4_AHB_dmac1_s_0x0_0x10000 0x10DC0300 0x10DC0358

Size: 64

Offset: 0x58

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RSVD_DMAC_CHx_AXI_QOSREG_8to63

RO 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD_DMAC_CHx_AXI_QOSREG_8to63

RO 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_DMAC_CHx_AXI_QOSREG_8to63

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_DMAC_CHx_AXI_QOSREG_8to63

RO 0x0

AXI_ARQOS

RW 0x0

AXI_AWQOS

RW 0x0

CH3_AXI_QOSREG Fields

Bit Name Description Access Reset
63:8 RSVD_DMAC_CHx_AXI_QOSREG_8to63 
DMAC Channelx AXI QOS Register (bits 8to63) Reserved bits - Read Only
 RO 0x0
7:4 AXI_ARQOS 
AXI ARQOS.
These bits form the arqos output of AXI4 master interface.
 RW 0x0
3:0 AXI_AWQOS 
AXI AWQOS.
These bits form the awqos output of AXI4 master interface.
 RW 0x0