CH2_STATUSREG 

         Channelx Status Register contains fields that indicate the status of DMA transfers for Channelx.
Module Instance Base Address Register Address
i_dma__dmac1_ahb_slv__10dc0000__Channel2_Registers_Address_Block__SEG_L4_AHB_dmac1_s_0x0_0x10000 0x10DC0200 0x10DC0230

Size: 64

Offset: 0x30

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RSVD_DMAC_CHx_STATUSREG_47to63

RO 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD_DMAC_CHx_STATUSREG_47to63

RO 0x0

DATA_LEFT_IN_FIFO

RO 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_DMAC_CHx_STATUSREG_22to31

RO 0x0

CMPLTD_BLK_TFR_SIZE

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CMPLTD_BLK_TFR_SIZE

RO 0x0

CH2_STATUSREG Fields

Bit Name Description Access Reset
63:47 RSVD_DMAC_CHx_STATUSREG_47to63 
DMAC Channelx Status Register (bits 47to63) Reserved bits - Read Only
 RO 0x0
46:32 DATA_LEFT_IN_FIFO 
Data Left in FIFO.
This bit indicates the total number of data left in DW_axi_dmac channel FIFO after completing the current block
transfer.
The width of the data in channel FIFO is equal to CHx_CTL.SRC_TR_WIDTH.
For normal block transfer completion without errors, Data_Left_In_FIFO = 0.
If any error occurs during the
dma transfer, the block transfer might be terminated early and in such a case, Data_Left_In_FIFO indicates the data remaining in channel FIFO which could not be transferred to destination
peripheral.
This field is cleared to zero on enabling the channel.
Note: If CHx_CTL.DST_TR_WIDTH > CHx_CTL.SRC_TR_WIDTH, there may be residual data left in the FIFO which is not
enough to form one CHx_CTL.SRC_TR_WIDTH of data and Data_Left_In_FIFO will return 0 in this case.
 RO 0x0
31:22 RSVD_DMAC_CHx_STATUSREG_22to31 
DMAC Channelx Status Register (bits 22to31) Reserved bits - Read Only
 RO 0x0
21:0 CMPLTD_BLK_TFR_SIZE 
Completed Block Transfer Size.
This bit indicates the total number of data of width CHx_CTL.SRC_TR_WIDTH transferred for the previous block
transfer.
For normal block transfer completion without any errors, this value will be equal to the value programmed in BLOCK_TS field of CHx_BLOCK_TS register.
If any error occurs during the
dma transfer, the block transfer might be terminated early and in such a case, this value indicates the actual data transferred without error in the current block.
This field is cleared to zero on enabling the channel.
 RO 0x0