CH2_AXI_IDREG 

         Channelx AXI ID Register. This register is allowed to be updated only when the channel is disabled, which means that it remains fixed for the entire
DMA transfer.
Note: The presence of this register is determined by the DMAC_M_ID_WIDTH and DMAC_NUM_CHANNELS configuration parameters.
 - If LLI is enabled for any of the channel, then the register is present only when:
DMAX_M_ID_WIDTH - (log2(DMAC_NUM_CHANNELS) +1) > 0
 - Otherwise:
DMAX_M_ID_WIDTH - log2(DMAC_NUM_CHANNELS) > 0
Module Instance Base Address Register Address
i_dma__dmac1_ahb_slv__10dc0000__Channel2_Registers_Address_Block__SEG_L4_AHB_dmac1_s_0x0_0x10000 0x10DC0200 0x10DC0250

Size: 64

Offset: 0x50

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RSVD_DMAC_CHx_AXI_IDREG_32to63

RO 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD_DMAC_CHx_AXI_IDREG_32to63

RO 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm32to63

RO 0x0

AXI_WRITE_ID_SUFFIX

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm1to31

RO 0x0

AXI_READ_ID_SUFFIX

RW 0x0

CH2_AXI_IDREG Fields

Bit Name Description Access Reset
63:32 RSVD_DMAC_CHx_AXI_IDREG_32to63 
DMAC Channelx AXI ID Register (bits 32to63) Reserved bits - Read Only
 RO 0x0
31:20 RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm32to63 
DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to32) Reserved bits - Read Only
 RO 0x0
19:16 AXI_WRITE_ID_SUFFIX 
AXI Write ID Suffix.
These bits form part of the AWID output of AXI3/AXI4 master interface.
     IDW = DMAX_M_ID_WIDTH
     L2NC =
log2(DMAX_NUM_CHANNELS)
The upper L2NC+1 bits of awidN is derived from the channel number which is currently accessing the master interface.
This varies for LLI fetch and source data
transfer.
For source data transfer, awidN for channel1 4'b0000, awidN for channel8 4'b0111 and so on.
For LLI fetch access, awidN for channel1 4'b1000, awidN for channel8 4'b1111 and so
on.
Lower bits are same as the value programmed in CHx_AXI_IDReg.AXI_Write_ID_Suffix filed.
 RW 0x0
15:4 RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm1to31 
DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to31) Reserved bits - Read Only
 RO 0x0
3:0 AXI_READ_ID_SUFFIX 
AXI Read ID Suffix
These bits form part of the ARID output of AXI3/AXI4 master interface.

     IDW = DMAX_M_ID_WIDTH

     L2NC = log2(DMAX_NUM_CHANNELS)

The upper L2NC+1 bits of aridN is derived from the channel number which is currently accessing the master interface.
This varies for LLI fetch and source data transfer.
For source data transfer,
aridN  for channel1 4'b0000, aridN for channel8 4'b0111 and so on.
For LLI fetch access, aridN  for channel1 4'b1000, aridN for channel8 4'b1111 and so on. Lower bits are same as the value programmed in CHx_AXI_IDReg.AXI_Read_ID_Suffix filed.
 RW 0x0