DMAC_INTSTATUSREG 

         DMAC Interrupt Status Register captures the combined channel interrupt for each channel and Combined common register block interrupt. This register is present provided number of DMA channels are greater than 8.
Module Instance Base Address Register Address
i_dma__dmac0_ahb_slv__10db0000__Common_Registers_Address_Block__SEG_L4_AHB_dmac0_s_0x0_0x10000 0x10DB0000 0x10DB0030

Size: 64

Offset: 0x30

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RSVD_DMAC_INTSTATUSREG_63to17

RO 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD_DMAC_INTSTATUSREG_63to17

RO 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_DMAC_INTSTATUSREG_63to17

RO 0x0

CommonReg_IntStat

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_DMAC_INTSTATUSREG

RO 0x0

CH8_IntStat

RO 0x0

CH7_IntStat

RO 0x0

CH6_IntStat

RO 0x0

CH5_IntStat

RO 0x0

CH4_IntStat

RO 0x0

CH3_IntStat

RO 0x0

CH2_IntStat

RO 0x0

CH1_IntStat

RO 0x0

DMAC_INTSTATUSREG Fields

Bit Name Description Access Reset
63:17 RSVD_DMAC_INTSTATUSREG_63to17 
DMAC Interrupt Status Register (bits 63to17) Reserved bits - Read Only
 RO 0x0
16 CommonReg_IntStat 
Common Register Interrupt Status Bit.
Value Description
0x0 Common Register Interrupt is Inactive
0x1 Common Register Interrupt is Active
RO 0x0
15:8 RSVD_DMAC_INTSTATUSREG 
DMAC Interrupt Status Register (bits 15to8) Reserved bits - Read Only
 RO 0x0
7 CH8_IntStat 
Channel 8 Interrupt Status Bit.
Value Description
0x0 Channel ${ch_num} Interrupt is Inactive
0x1 Channel ${ch_num} Interrupt is Active
RO 0x0
6 CH7_IntStat 
Channel 7 Interrupt Status Bit.
Value Description
0x0 Channel ${ch_num} Interrupt is Inactive
0x1 Channel ${ch_num} Interrupt is Active
RO 0x0
5 CH6_IntStat 
Channel 6 Interrupt Status Bit.
Value Description
0x0 Channel ${ch_num} Interrupt is Inactive
0x1 Channel ${ch_num} Interrupt is Active
RO 0x0
4 CH5_IntStat 
Channel 5 Interrupt Status Bit.
Value Description
0x0 Channel ${ch_num} Interrupt is Inactive
0x1 Channel ${ch_num} Interrupt is Active
RO 0x0
3 CH4_IntStat 
Channel 4 Interrupt Status Bit.
Value Description
0x0 Channel ${ch_num} Interrupt is Inactive
0x1 Channel ${ch_num} Interrupt is Active
RO 0x0
2 CH3_IntStat 
Channel 3 Interrupt Status Bit.
Value Description
0x0 Channel ${ch_num} Interrupt is Inactive
0x1 Channel ${ch_num} Interrupt is Active
RO 0x0
1 CH2_IntStat 
Channel 2 Interrupt Status Bit.
Value Description
0x0 Channel ${ch_num} Interrupt is Inactive
0x1 Channel ${ch_num} Interrupt is Active
RO 0x0
0 CH1_IntStat 
Channel 1 Interrupt Status Bit.
Value Description
0x0 Channel ${ch_num} Interrupt is Inactive
0x1 Channel ${ch_num} Interrupt is Active
RO 0x0