DMAC_COMMONREG_INTSTATUSREG

         This Register captures Slave interface access errors.
 - Decode Error.
 - Write to read only register. 
 - Read to write only register.
 - write on hold.
 - undefined address.
 - Common Register Space - Write Parity Error


Module Instance	Base Address	Register Address
`i_dma__dmac0_ahb_slv__10db0000__Common_Registers_Address_Block__SEG_L4_AHB_dmac0_s_0x0_0x10000`	`0x10DB0000`	`0x10DB0050`

Size: 64

Offset: 0x50

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
`RSVD_DMAC_COMMONREG_INTSTATUSREG_63to21` `RO 0x0`
47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
`RSVD_DMAC_COMMONREG_INTSTATUSREG_63to21` `RO 0x0`
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_DMAC_COMMONREG_INTSTATUSREG_63to21` `RO 0x0`											`MXIF2_BCH_EccPROT_UnCorrERR_IntStat` `RO 0x0`	`MXIF2_BCH_EccPROT_CorrERR_IntStat` `RO 0x0`	`MXIF2_RCH1_EccPROT_UnCorrERR_IntStat` `RO 0x0`	`MXIF2_RCH1_EccPROT_CorrERR_IntStat` `RO 0x0`	`MXIF2_RCH0_EccPROT_UnCorrERR_IntStat` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`MXIF2_RCH0_EccPROT_CorrERR_IntStat` `RO 0x0`	`MXIF1_BCH_EccPROT_UnCorrERR_IntStat` `RO 0x0`	`MXIF1_BCH_EccPROT_CorrERR_IntStat` `RO 0x0`	`MXIF1_RCH1_EccPROT_UnCorrERR_IntStat` `RO 0x0`	`MXIF1_RCH1_EccPROT_CorrERR_IntStat` `RO 0x0`	`MXIF1_RCH0_EccPROT_UnCorrERR_IntStat` `RO 0x0`	`MXIF1_RCH0_EccPROT_CorrERR_IntStat` `RO 0x0`	`SLVIF_UndefinedReg_DEC_ERR_IntStat` `RO 0x0`	`SLVIF_CommonReg_WRPARITY_ERR_IntStat` `RO 0x0`	`RSVD_DMAC_COMMONREG_INTSTATUSREG_6to4` `RO 0x0`			`SLVIF_CommonReg_WrOnHold_ERR_IntStat` `RO 0x0`	`SLVIF_CommonReg_RD2WO_ERR_IntStat` `RO 0x0`	`SLVIF_CommonReg_WR2RO_ERR_IntStat` `RO 0x0`	`SLVIF_CommonReg_DEC_ERR_IntStat` `RO 0x0`

DMAC_COMMONREG_INTSTATUSREG Fields

Bit Name Description Access Reset

63:21

RSVD_DMAC_COMMONREG_INTSTATUSREG_63to21

DMAC Common Register Interrupt Signal Enable Register (bits 63to21) Reserved bits - Read Only

RO

0x0

MXIF2_BCH_EccPROT_UnCorrERR_IntStat

   AXI Master Interface 2 Write Response Channel ECC Protection Uncorrectable Error Interrupt Status bit.

   This error occurs if ECC Uncorrectable error is detected on the AXI Channel Write Response payload. 

 - 0: No AXI Master 2 Write Response Channel Uncorrectable Error.
 - 1: AXI Master 2 Write Response Channel Uncorrectable Error detected.

Error Interrupt status is generated if the corresponding Status Enable bit in DMAC_COMMONREG_INTSTATUS_ENABLEREG register is set to 1. This bit is cleared to 0 on writing 1 to the corresponding interrupt clear bit in DMAC_COMMONREG_INTCLEARREG.

Value	Description
0x0	AXI Master 2 Write Response Channel Uncorrectable Error not detected
0x1	AXI Master 2 Write Response Channel Uncorrectable Error detected

RO

0x0

MXIF2_BCH_EccPROT_CorrERR_IntStat

   AXI Master Interface 2 Write Response Channel ECC Protection Correctable Error Interrupt Status bit.

   This error occurs if ECC Correctable error is detected on the AXI Channel Write Response payload. 

 - 0: No AXI Master 2 Write Response Channel Correctable Error.
 - 1: AXI Master 2 Write Response Channel Correctable Error detected.

Error Interrupt status is generated if the corresponding Status Enable bit in DMAC_COMMONREG_INTSTATUS_ENABLEREG register is set to 1. This bit is cleared to 0 on writing 1 to the corresponding interrupt clear bit in DMAC_COMMONREG_INTCLEARREG.

Value	Description
0x0	AXI Master 2 Write Response Channel Correctable Error not detected
0x1	AXI Master 2 Write Response Channel Correctable Error detected

RO

0x0

MXIF2_RCH1_EccPROT_UnCorrERR_IntStat

   AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection Uncorrectable Error Interrupt Status bit.

   This error occurs if ECC Uncorrectable error is detected on the AXI Channel Read Control payload. 

 - 0: No AXI Master 2 Read Channel Control signals related Uncorrectable Error.
 - 1: AXI Master 2 Read Channel Control signals related Uncorrectable Error detected.

Error Interrupt status is generated if the corresponding Status Enable bit in DMAC_COMMONREG_INTSTATUS_ENABLEREG register is set to 1. This bit is cleared to 0 on writing 1 to the corresponding interrupt clear bit in DMAC_COMMONREG_INTCLEARREG.

Value	Description
0x0	AXI Master 2 Read Channel (Other Control signals) Uncorrectable Error not detected
0x1	AXI Master 2 Read Channel (Other Control signals) Uncorrectable Error detected

RO

0x0

MXIF2_RCH1_EccPROT_CorrERR_IntStat

   AXI Master Interface 2 Read Channel (Other Control signals) ECC Protection Correctable Error Interrupt Status bit.

   This error occurs if ECC Correctable error is detected on the AXI Channel Read Control payload. 

 - 0: No AXI Master 2 Read Channel Control signlas related Correctable Error.
 - 1: AXI Master 2 Read Channel Control signals related Correctable Error detected.

Error Interrupt status is generated if the corresponding Status Enable bit in DMAC_COMMONREG_INTSTATUS_ENABLEREG register is set to 1. This bit is cleared to 0 on writing 1 to the corresponding interrupt clear bit in DMAC_COMMONREG_INTCLEARREG.

Value	Description
0x0	AXI Master 2 Read Channel (Other Control signals) Correctable Error not detected
0x1	AXI Master 2 Read Channel (Other Control signals) Correctable Error detected

RO

0x0

MXIF2_RCH0_EccPROT_UnCorrERR_IntStat

   AXI Master Interface 2 Read Channel (Data) ECC Protection Uncorrectable Error Interrupt Status bit.

   This error occurs if ECC Uncorrectable error is detected on the AXI Channel Read Data payload. 

 - 0: No AXI Master 2 Read Channel Data related Uncorrectable Error.
 - 1: AXI Master 2 Read Channel Data related Uncorrectable Error detected.

Error Interrupt status is generated if the corresponding Status Enable bit in DMAC_COMMONREG_INTSTATUS_ENABLEREG register is set to 1. This bit is cleared to 0 on writing 1 to the corresponding interrupt clear bit in DMAC_COMMONREG_INTCLEARREG.

Value	Description
0x0	AXI Master 2 Read Channel (Data) Uncorrectable Error not detected
0x1	AXI Master 2 Read Channel (Data) Uncorrectable Error detected

RO

0x0

MXIF2_RCH0_EccPROT_CorrERR_IntStat

   AXI Master Interface 2 Read Channel (Data) ECC Protection Correctable Error Interrupt Status bit.

   This error occurs if ECC Correctable error is detected on the AXI Channel Read Data payload. 

 - 0: No AXI Master 2 Read Channel Data related Correctable Error.
 - 1: AXI Master 2 Read Channel Data related Correctable Error detected.

Error Interrupt status is generated if the corresponding Status Enable bit in DMAC_COMMONREG_INTSTATUS_ENABLEREG register is set to 1. This bit is cleared to 0 on writing 1 to the corresponding interrupt clear bit in DMAC_COMMONREG_INTCLEARREG.

Value	Description
0x0	AXI Master 2 Read Channel (Data) Correctable Error not detected
0x1	AXI Master 2 Read Channel (Data) Correctable Error detected

RO

0x0

MXIF1_BCH_EccPROT_UnCorrERR_IntStat

   AXI Master Interface 1 Write Response Channel ECC Protection Uncorrectable Error Interrupt Status bit.

   This error occurs if ECC Uncorrectable error is detected on the AXI Channel Write Response payload. 

 - 0: No AXI Master 1 Write Response Channel Uncorrectable Error.
 - 1: AXI Master 1 Write Response Channel Uncorrectable Error detected.

Error Interrupt status is generated if the corresponding Status Enable bit in DMAC_COMMONREG_INTSTATUS_ENABLEREG register is set to 1. This bit is cleared to 0 on writing 1 to the corresponding interrupt clear bit in DMAC_COMMONREG_INTCLEARREG.

Value	Description
0x0	AXI Master 1 Write Response Channel Uncorrectable Error not detected
0x1	AXI Master 1 Write Response Channel Uncorrectable Error detected

RO

0x0

MXIF1_BCH_EccPROT_CorrERR_IntStat

   AXI Master Interface 1 Write Response Channel ECC Protection Correctable Error Interrupt Status bit.

   This error occurs if ECC Correctable error is detected on the AXI Channel Write Response payload. 

 - 0: No AXI Master 1 Write Response Channel Correctable Error.
 - 1: AXI Master 1 Write Response Channel Correctable Error detected.

Error Interrupt status is generated if the corresponding Status Enable bit in DMAC_COMMONREG_INTSTATUS_ENABLEREG register is set to 1. This bit is cleared to 0 on writing 1 to the corresponding interrupt clear bit in DMAC_COMMONREG_INTCLEARREG.

Value	Description
0x0	AXI Master 1 Write Response Channel Correctable Error not detected
0x1	AXI Master 1 Write Response Channel Correctable Error detected

RO

0x0

MXIF1_RCH1_EccPROT_UnCorrERR_IntStat

   AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection Uncorrectable Error Interrupt Status bit.

   This error occurs if ECC Uncorrectable error is detected on the AXI Channel Read Control payload. 

 - 0: No AXI Master 1 Read Channel Control signals related Uncorrectable Error.
 - 1: AXI Master 1 Read Channel Control signals related Uncorrectable Error detected.

Error Interrupt status is generated if the corresponding Status Enable bit in DMAC_COMMONREG_INTSTATUS_ENABLEREG register is set to 1. This bit is cleared to 0 on writing 1 to the corresponding interrupt clear bit in DMAC_COMMONREG_INTCLEARREG.

Value	Description
0x0	AXI Master 1 Read Channel (Other Control signals) Uncorrectable Error not detected
0x1	AXI Master 1 Read Channel (Other Control signals) Uncorrectable Error detected

RO

0x0

MXIF1_RCH1_EccPROT_CorrERR_IntStat

   AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection Correctable Error Interrupt Status bit.

   This error occurs if ECC Correctable error is detected on the AXI Channel Read Control payload. 

 - 0: No AXI Master 1 Read Channel Control signlas related Correctable Error.
 - 1: AXI Master 1 Read Channel Control signals related Correctable Error detected.

Error Interrupt status is generated if the corresponding Status Enable bit in DMAC_COMMONREG_INTSTATUS_ENABLEREG register is set to 1. This bit is cleared to 0 on writing 1 to the corresponding interrupt clear bit in DMAC_COMMONREG_INTCLEARREG.

Value	Description
0x0	AXI Master 1 Read Channel (Other Control signals) Correctable Error not detected
0x1	AXI Master 1 Read Channel (Other Control signals) Correctable Error detected

RO

0x0

MXIF1_RCH0_EccPROT_UnCorrERR_IntStat

   AXI Master Interface 1 Read Channel (Data) ECC Protection Uncorrectable Error Interrupt Status bit.

   This error occurs if ECC Uncorrectable error is detected on the AXI Channel Read Data payload. 

 - 0: No AXI Master 1 Read Channel Data related Uncorrectable Error.
 - 1: AXI Master 1 Read Channel Data related Uncorrectable Error detected.

Error Interrupt status is generated if the corresponding Status Enable bit in DMAC_COMMONREG_INTSTATUS_ENABLEREG register is set to 1. This bit is cleared to 0 on writing 1 to the corresponding interrupt clear bit in DMAC_COMMONREG_INTCLEARREG.

Value	Description
0x0	AXI Master 1 Read Channel (Data) Uncorrectable Error not detected
0x1	AXI Master 1 Read Channel (Data) Uncorrectable Error detected

RO

0x0

MXIF1_RCH0_EccPROT_CorrERR_IntStat

   AXI Master Interface 1 Read Channel (Data) ECC Protection Correctable Error Interrupt Status bit.

   This error occurs if ECC Correctable error is detected on the AXI Channel Read Data payload. 

 - 0: No AXI Master 1 Read Channel Data related Correctable Error.
 - 1: AXI Master 1 Read Channel Data related Correctable Error detected.

Error Interrupt status is generated if the corresponding Status Enable bit in DMAC_COMMONREG_INTSTATUS_ENABLEREG register is set to 1. This bit is cleared to 0 on writing 1 to the corresponding interrupt clear bit in DMAC_COMMONREG_INTCLEARREG.

Value	Description
0x0	AXI Master 1 Read Channel (Data) Correctable Error not detected
0x1	AXI Master 1 Read Channel (Data) Correctable Error detected

RO

0x0

SLVIF_UndefinedReg_DEC_ERR_IntStat

Slave Interface Undefined register Decode Error Interrupt Signal Enable Bit.
Decode Error generated by DW_axi_dmac during register access. This error occurs if the register access is to undefined address range (>0x8FF if 8 channels are configured, >0x4FF if 4 channels are configured etc.) resulting in error response by DW_axi_dmac slave interface. 
 - 0: No Slave Interface Decode Errors.
 - 1: Slave Interface Decode Error detected.
Error Interrupt Status is generated if the corresponding Status Enable bit in DMAC_CommonReg_IntStatus_Enable register bit is set to 1. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in DMAC_COMMONREG_INTCLEARREG on enabling the channel (required when the interrupt is not enabled).

Value	Description
0x0	No Slave Interface Decode Errors
0x1	Slave Interface Decode Error detected

RO

0x0

SLVIF_CommonReg_WRPARITY_ERR_IntStat

Slave Interface Common Register Write Parity Error Interrupt Status Bit.
This error occurs if write operation with data and parity is performed to a register in the common register space, but the locally computed parity bits not matching the received parity bits. 
 - 0: No Common Register Space Write Parity Error.
 - 1: Common Register Space Write Parity Error detected.
Error Interrupt Status is generated if the corresponding Status Enable bit in DMAC_CommonReg_IntStatus_Enable register bit is set to 1. This bit is cleared to 0 on writing 1 to the corresponding interrupt clear bit in DMAC_COMMONREG_INTCLEARREG (required when the interrupt is not enabled.

Value	Description
0x0	No Slave Interface Common Register Write Parity Errors
0x1	Slave Interface Common Register Write Parity Error detected

RO

0x0

6:4

RSVD_DMAC_COMMONREG_INTSTATUSREG_6to4

DMAC Common Register Interrupt Status Register (bits 6to4) Reserved bits - Read Only

RO

0x0

SLVIF_CommonReg_WrOnHold_ERR_IntStat

Slave Interface Common Register Write On Hold Error Interrupt Status Bit.
This error occurs if an illegal write operation is performed on a common register; this happens if a write operation is performed on a common register except DMAC_RESETREG with DMAC_RST field set to 1 when DW_axi_dmac is in Hold mode. 
 - 0: No Slave Interface Common Register Write On Hold Errors.
 - 1: Slave Interface Common Register Write On Hold Error detected.
Error Interrupt Status is generated if the corresponding Status Enable bit in DMAC_CommonReg_IntStatus_Enable register bit is set to 1. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in DMAC_COMMONREG_INTCLEARREG on enabling the channel (required when the interrupt is not enabled).

Value	Description
0x0	No Slave Interface Common Register Write On Hold Errors
0x1	Slave Interface Common Register Write On Hold Error detected

RO

0x0

SLVIF_CommonReg_RD2WO_ERR_IntStat

Slave Interface Common Register Read to Write only Error Interrupt Status bit.
This error occurs if Read operation is performed to a Write Only register in the common register space (0x000 to 0x0FF). 
 - 0: No Slave Interface Read to Write Only Errors.
 - 1: Slave Interface Read to Write Only Error detected.
Error Interrupt status is generated if the corresponding Status Enable bit in DMAC_CommonReg_IntStatus_Enable register bit is set to 1. This bit is cleared to 0 on writing 1 to the corresponding
channel interrupt clear bit in DMAC_COMMONREG_INTCLEARREG on enabling the channel (required when the interrupt is not enabled).

Value	Description
0x0	No Slave Interface Read to Write Only Errors
0x1	Slave Interface Read to Write Only Error detected

RO

0x0

SLVIF_CommonReg_WR2RO_ERR_IntStat

Slave Interface Common Register Write to Read Only Error Interrupt Status bit.
This error occurs if write operation is performed to a Read Only register in the common register space (0x000 to 0x0FF). 
 - 0: No Slave Interface Write to Read Only Errors.
 - 1: Slave Interface Write to Read Only Error detected.
Error Interrupt status is generated if the corresponding Status Enable bit in DMAC_CommonReg_IntStatus_Enable register bit is set to 1. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in DMAC_COMMONREG_INTCLEARREG on enabling the channel (required when the interrupt is not enabled).

Value	Description
0x0	Slave Interface Write to Read Only Error detected
0x1	No Slave Interface Write to Read Only Errors

RO

0x0

SLVIF_CommonReg_DEC_ERR_IntStat

Slave Interface Common Register Decode Error Interrupt Status Bit.
Decode Error generated by DW_axi_dmac during register access. This error occurs if
the register access is to an invalid address in the common register space (0x000 to 0x0FF) resulting in error response by DW_axi_dmac slave interface.
 - 0: No Slave Interface Decode Errors.
 - 1: Slave Interface Decode Error detected.
The Error Interrupt status is generated if the corresponding Status Enable bit in DMAC_CommonReg_IntStatus_Enable register bit is set to 1. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in DMAC_COMMONREG_INTCLEARREG on enabling the channel (required when the interrupt is not enabled).

Value	Description
0x0	No Slave Interface Decode Errors
0x1	Slave Interface Decode Error detected

RO

0x0