DMAC_CFGREG

         This register is used to enable the DW_axi_dmac, which must be done before any channel
activity can begin. This register also contains global interrupt enable bit.


Module Instance	Base Address	Register Address
`i_dma__dmac0_ahb_slv__10db0000__Common_Registers_Address_Block__SEG_L4_AHB_dmac0_s_0x0_0x10000`	`0x10DB0000`	`0x10DB0010`

Size: 64

Offset: 0x10

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
`RSVD_DMAC_CFGREG` `RO 0x0`
47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
`RSVD_DMAC_CFGREG` `RO 0x0`
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_DMAC_CFGREG` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_DMAC_CFGREG` `RO 0x0`														`INT_EN` `RW 0x0`	`DMAC_EN` `RW 0x0`

DMAC_CFGREG Fields

Bit Name Description Access Reset

63:2

RSVD_DMAC_CFGREG

DMAC_CFGREG Reserved bits - Read Only

RO

0x0

INT_EN

This bit is used to globally enable the interrupt generation.
 - 0: DW_axi_dmac Interrupts are disabled
 - 1: DW_axi_dmac Interrupt logic is enabled.

Value	Description
0x0	DW_axi_dmac Interrupts are disabled
0x1	DW_axi_dmac Interrupts are enabled

RW

0x0

DMAC_EN

This bit is used to enable the DW_axi_dmac.
 - 0: DW_axi_dmac disabled
 - 1: DW_axi_dmac enabled
NOTE: If this bit DMAC_EN bit is cleared while any channel is still active, then this bit still returns 1 to indicate that there are channels still active until DW_axi_dmac hardware has
terminated all activity on all channels, at which point this bit returns zero (0).

Value	Description
0x0	DW_axi_dmac is disabled
0x1	DW_axi_dmac is enabled

RW

0x0