CH4_LLP

         This is the Linked List Pointer register. This register must be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the
channel if linked-list-based block chaining is enabled. This register is updated with new value of linked list pointer during the LLI update stage of dma transfer.


Module Instance	Base Address	Register Address
`i_dma__dmac0_ahb_slv__10db0000__Channel4_Registers_Address_Block__SEG_L4_AHB_dmac0_s_0x0_0x10000`	`0x10DB0400`	`0x10DB0428`

Size: 64

Offset: 0x28

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
`LOC` `RW 0x0`
47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
`LOC` `RW 0x0`
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`LOC` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`LOC` `RW 0x0`										`RSVD_DMAC_CHx_LLP_1to5` `RO 0x0`					`LMS` `RO 0x0`

CH4_LLP Fields

Bit Name Description Access Reset

63:6

LOC

Starting Address Memory of LLI block
Starting Address In Memory of next LLI if block chaining is enabled. The six LSBs of the starting address
are not stored because the address is assumed to be aligned to a 64-byte boundary.
LLI access always uses the burst size (arsize/awsize) that is same as the data bus width and cannot be changed or
programmed to anything other than this. Burst length (awlen/arlen) is chosen based on the data bus width so that the access does not cross one complete LLI structure of 64 bytes. DW_axi_dmac will fetch
the entire LLI (40 bytes) in one AXI burst if the burst length is not limited by other settings.

RW

0x0

5:1

RSVD_DMAC_CHx_LLP_1to5

DMAC Channelx Linked List Pointer Register (bits 1to5) Reserved bits - Read Only

RO

0x0

LMS

LLI master Select
This bit identifies the AXI layer/interface where the memory device that stores the next linked list item resides. 
 - 0: AXI Master 1
 - 1: AXI Master 2
This field does not exist if the configuration parameter DMAX_CHx_LMS is not set to NO_HARDCODE.
In this case, the read-back value is always the hardcoded value. The maximum value of this field that can be read back is 'DMAX_NUM_MASTER_IF-1'.

Value	Description
0x0	next Linked List item resides on AXI Master1 interface
0x1	next Linked List item resides on AXI Master2 interface

RO

0x0