CH4_DAR 

         The starting destination address is programmed by the software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer.
While the DMA transfer is in progress, this register is updated to reflect the destination address of the current AXI transfer.
Module Instance Base Address Register Address
i_dma__dmac0_ahb_slv__10db0000__Channel4_Registers_Address_Block__SEG_L4_AHB_dmac0_s_0x0_0x10000 0x10DB0400 0x10DB0408

Size: 64

Offset: 0x8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

DAR

RW 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

DAR

RW 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DAR

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DAR

RW 0x0

CH4_DAR Fields

Bit Name Description Access Reset
63:0 DAR 
Current Destination Address of DMA transfer.
Updated after each destination transfer. The DINC fields in the CHx_CTL register determines whether the address increments or is left unchanged on every destination transfer throughout the block transfer.
 RW 0x0