CH3_BLOCK_TS
When DW_axi_dmac is the flow controller, the DMAC uses this register before the channel is enabled for block-size.
Module Instance | Base Address | Register Address |
---|---|---|
i_dma__dmac0_ahb_slv__10db0000__Channel3_Registers_Address_Block__SEG_L4_AHB_dmac0_s_0x0_0x10000
|
0x10DB0300
|
0x10DB0310
|
Size: 64
Offset: 0x10
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
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47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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CH3_BLOCK_TS Fields
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
63:22 |
RSVD_DMAC_CHx_BLOCK_TSREG_63to22
|
DMAC Channelx Block Transfer Size Register (bits 63to22) Reserved bits - Read Only |
RO
|
0x0
|
21:0 |
BLOCK_TS
|
Block Transfer Size. The number programmed into BLOCK_TS field indicates the total number of data of width CHx_CTL.SRC_TR_WIDTH to be transferred in a DMA block transfer. Block Transfer Size = BLOCK_TS+1 When the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of who is the flow controller. When the source or destination peripheral is assigned as the flow controller, the value before the transfer starts saturates at DMAX_CHx_MAX_BLK_SIZE, but the actual block size can be greater. |
RW
|
0x0
|