enable
Enable
Module Instance | Base Address | Register Address |
---|---|---|
soc_mpfe_fw_tbu2noc_inst_0__fw_ddr_fpga2sdram__18000c00__ddr_scr__DDR_SCR
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0x18000C00
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0x18000C00
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Size: 32
Offset: 0x
Access: RW
Access mode: SECURE | PRIVILEGEMODE
Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.
Bit Fields | |||||||||||||||
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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enable Fields
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
31:8 |
Reserved_8
|
Reserved bitfield added by Magillem |
RO
|
0x0
|
7 |
region7enable
|
Region 7 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW
|
0x0
|
6 |
region6enable
|
Region 6 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW
|
0x0
|
5 |
region5enable
|
Region 5 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW
|
0x0
|
4 |
region4enable
|
Region 4 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW
|
0x0
|
3 |
region3enable
|
Region 3 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW
|
0x0
|
2 |
region2enable
|
Region 2 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW
|
0x0
|
1 |
region1enable
|
Region 1 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW
|
0x0
|
0 |
region0enable
|
Region 0 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW
|
0x0
|