XAIUTOPCR00

         XAIU Trace Trigger Opcode Register


Module Instance	Base Address	Register Address
`i_ccu__DSU__1c000000__CCU_IOM`	`0x1C004000`	`0x1C004810`

Size: 32

Offset: 0x810

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`valid2` `RW 0x0`	`opcode2` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`valid1` `RW 0x0`	`opcode1` `RW 0x0`

XAIUTOPCR00 Fields


Bit	Name	Description	Access	Reset
31	`valid2`	Valid 2	`RW`	`0x0`
30:16	`opcode2`	Opcode 2	`RW`	`0x0`
15	`valid1`	Valid 1	`RW`	`0x0`
14:0	`opcode1`	Opcode 1	`RW`	`0x0`