XAIUQOSSR

         XAIU QoS Status Register


Module Instance	Base Address	Register Address
`i_ccu__DSU__1c000000__CCU_IOM`	`0x1C004000`	`0x1C004204`

Size: 32

Offset: 0x204

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Rsvd2` `RO 0x0`												`EventStatusCount` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`EventStatusCount` `RW 0x0`												`Rsvd1` `RO 0x0`		`EventStatusCountOverflow` `RW 0x0`	`EventStatus` `RO 0x0`

XAIUQOSSR Fields


Bit	Name	Description	Access	Reset
31:20	`Rsvd2`	Reserved	`RO`	`0x0`
19:4	`EventStatusCount`	Counts number of times event threshold was hit	`RW`	`0x0`
3:2	`Rsvd1`	Reserved	`RO`	`0x0`
1	`EventStatusCountOverflow`	Event count overflow bit, this bit is set once the counter overflows	`RW`	`0x0`
0	`EventStatus`	0: Normal Mode 1: Starvation Mode	`RO`	`0x0`