XAIUCNTCR3

         PMON Counter Control Register


Module Instance	Base Address	Register Address
`i_ccu__DSU__1c000000__CCU_IOM`	`0x1C004000`	`0x1C004B30`

Size: 32

Offset: 0xB30

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Rsvd1` `RO 0x0`		`CntEvtFirst` `RW 0x0`						`Rsvd0` `RO 0x0`		`CntEvtSecond` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`MinStallPeriod` `RW 0x0`			`FilterSel` `RW 0x0`			`SSRCount` `RW 0x0`			`CounterCtl` `RW 0x0`			`OverFlowStatus` `RO 0x0`	`InterruptEn` `RW 0x0`	`CountClr` `RW 0x0`	`CountEn` `RW 0x0`

XAIUCNTCR3 Fields


Bit	Name	Description	Access	Reset
31:30	`Rsvd1`	Reserved bis 31:30	`RO`	`0x0`
29:24	`CntEvtFirst`	Select the first count event, 0 not valid	`RW`	`0x0`
23:22	`Rsvd0`	Reserved bis 23:22	`RO`	`0x0`
21:16	`CntEvtSecond`	Select the second count event, 0 not valid	`RW`	`0x0`
15:13	`MinStallPeriod`	value is (2^ minstallperiod)	`RW`	`0x0`
12:10	`FilterSel`	LPF coefficients	`RW`	`0x0`
9:7	`SSRCount`	000: clear CNTSR, 001: capture upper bits in CNTSR, 010: use CNTSR as LPF, 011: use CNTSR as max/saturation	`RW`	`0x0`
6:4	`CounterCtl`	Counter mode. 000: Normal, 001: AND, 010: XOR	`RW`	`0x0`
3	`OverFlowStatus`	Indicates overflow, sticky bit clears by clearing the counter	`RO`	`0x0`
2	`InterruptEn`	Enable rollover or overflow interrupt	`RW`	`0x0`
1	`CountClr`	Clear counter	`RW`	`0x0`
0	`CountEn`	Enable counting	`RW`	`0x0`