DMIUSMCAPR

         DMIU System Memory Cache Allocation Policy Register


Module Instance	Base Address	Register Address
`i_ccu__DSU__1c000000__CCU_DMI1`	`0x1C008000`	`0x1C008308`

Size: 32

Offset: 0x308

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Rsvd1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Rsvd1` `RO 0x0`											`WrAllocDisable` `RW 0x0`	`RdAllocDisable` `RW 0x0`	`DtyWrAllocDisable` `RW 0x0`	`ClnWrAllocDisable` `RW 0x0`	`TOFAllocDisable` `RW 0x0`

DMIUSMCAPR Fields


Bit	Name	Description	Access	Reset
31:5	`Rsvd1`	Reserved	`RO`	`0x0`
4	`WrAllocDisable`	This bit disables cache allocation for writes	`RW`	`0x0`
3	`RdAllocDisable`	This bit disables cache allocation for reads	`RW`	`0x0`
2	`DtyWrAllocDisable`	This bit disables cache allocation for dirty writes	`RW`	`0x0`
1	`ClnWrAllocDisable`	This bit disables cache allocation for clean writes	`RW`	`0x0`
0	`TOFAllocDisable`	This bit disables cache allocation for writeUnique from CHI/ACE processors	`RW`	`0x0`