DMIUCESR 

         DMIU Correctable Error Status Register
Module Instance Base Address Register Address
i_ccu__DSU__1c000000__CCU_DMI1 0x1C008000 0x1C008144

Size: 32

Offset: 0x144

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ErrInfo

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ErrType

RO 0x0

Rsvd1

RO 0x0

ErrCount

RO 0x0

ErrCountOverflow

RO 0x0

ErrVld

RW 0x0

DMIUCESR Fields

Bit Name Description Access Reset
31:16 ErrInfo 
This field indicates additional information about logged error type, if the Correctable Error Valid bit is set.
            If it is a data SRAM correctable error then
            bits 1:0   2'b10 represent write buffer (2'b00, 2'b01 and 2'b11: reserved)
            bits 15:2  Reserved
            If it is a cache SRAM correctable error then
            bit  0     1'b0 Tag Array 1'b1 Data Array
            bits 15:1  Reserved
 RO 0x0
15:12 ErrType 
This field indicates the logged error type, if the Correctable Error Valid bit is set.
            0x00: Data SRAM uncorrectable error
            0x01: Cache SRAM uncorrectable error
            All other encodings are reserved
 RO 0x0
11:10 Rsvd1 
Reserved
 RO 0x0
9:2 ErrCount 
This field indicates the number of correctable errors detected by the unit. The field stops incrementing if the Correctable Error Count Overflow bit is set
 RO 0x0
1 ErrCountOverflow 
This bit indicates that the number of correctable errors detected by the unit overflowed the Correctable Error Count field
 RO 0x0
0 ErrVld 
If this bit is set, Error information is logged in status and location registers. Writing a one to the Correctable Error Valid bit clears the Correctable Error Valid bit.
 RW 0x0