DMA_Mode 

         The Bus Mode register establishes the bus operating modes for the DMA.
Module Instance Base Address Register Address
u_emac2__apb_reg_config_slave__10830000__DWCXG_DMA__SEG_L4_MP_emac2_s_0x0_0x10000 0x10833000 0x10833000

Size: 32

Offset: 0x

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_31_14

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_31_14

RO 0x0

INTM

RW 0x0

Reserved_11_9

RO 0x0

DSPW

RW 0x0

Reserved_7_6

RO 0x0

Reserved_TMRP

RO 0x0

TDRP

RW 0x0

Reserved_3_1

RO 0x0

SWR

RW 0x0

DMA_Mode Fields

Bit Name Description Access Reset
31:14 Reserved_31_14 
Reserved.
 RO 0x0
13:12 INTM 
Interrupt Mode.
  
  This field controls the behavior of the interrupt signal (sbd_intr_o, sbd_perch_tx_intr_o, sbd_perch_rx_intr_o) outputs for packet transfer completion events in TxDMA and RxDMA.
   - 00: sbd_perch_* are pulse signals for each completion events. sbd_intr_o is also asserted and cleared only when software clears the corresponding RI/TI status bits.
   - 01: sbd_perch_* are level signals asserted on the corresponding event and de-asserted when the software clears the corresponding RI/TI status bits. The sbd_intr_o is not asserted for these packet transfer completion events.
   - 10: sbd_perch_* are level signals asserted on the corresponding event and de-asserted when the software clears the corresponding RI/TI status bits. However, the signal is asserted again if the same event occurred again before it was cleared. The sbd_intr_o is not asserted for these packet transfer completion events.
   - 11: Reserved 
  For more details see Table, "DWC_xgmac Transfer Complete Interrupt Behavior"
 RW 0x0
11:9 Reserved_11_9 
Reserved.
 RO 0x0
8 DSPW 
Descriptor Posted Write.
   - 0: By default, all Rx DMA descriptor writes are non-posted and any Rx interrupt generation mechanism can be used, that is, Descriptor IOC, Watchdog timer, Byte Counter based or any combination of these. 
   - 1: All Rx DMA data and descriptor writes are posted and Descriptor IOC based Rx interrupt generation does not function properly and must not be used. Only Watchdog timer, Byte Counter based or any combination of these Rx interrupt generation mechanisms must be used. The Tx/Rx DMA Descriptor IOC based Tx/Rx interrupt generation mechanism does not function properly and must not be used.
 RW 0x0
7:6 Reserved_7_6 
Reserved.
 RO 0x0
5 Reserved_TMRP 
Reserved.
 RO 0x0
4 TDRP 
Tx Descriptor Read Priority.
  
  This bit controls the arbitration priority of descriptor fetches from the local cache when simultaneous requests are generated from RxDMA and TxDMA channels. 
  
  By default, when this bit is 0, the RxDMA requests get higher priority. 
  
  When this bit is set to 1, TxDMA descriptor fetches are serviced first by the arbiter before the RxDMA requests.
 RW 0x0
3:1 Reserved_3_1 
Reserved.
 RO 0x0
0 SWR 
Software Reset.
  
  When this bit is set, the MAC and the DMA controller reset the logic and all internal registers of the DMA, MTL, and MAC. This bit is automatically cleared after the reset operation is complete in all DWC_xgmac clock domains. Before reprogramming any DWC_xgmac register, read a value of 0 from this bit.
  
  Note:  The reset operation is complete only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock.
 RW 0x0