DMA_CH3_Status 

         The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA.
Module Instance Base Address Register Address
u_emac1__apb_reg_config_slave__10820000__DWCXG_DMA_CH3__SEG_L4_MP_emac1_s_0x0_0x10000 0x10823280 0x108232E0

Size: 32

Offset: 0x60

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_31_22

RO 0x0

REB

RW 0x0

TEB

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NIS

RW 0x0

AIS

RW 0x0

CDE

RW 0x0

FBE

RW 0x0

Reserved_11_10

RO 0x0

DDE

RW 0x0

RPS

RW 0x0

RBU

RW 0x0

RI

RW 0x0

Reserved_5_3

RO 0x0

TBU

RW 0x0

TPS

RW 0x0

TI

RW 0x0

DMA_CH3_Status Fields

Bit Name Description Access Reset
31:22 Reserved_31_22 
Reserved.
 RO 0x0
21:19 REB 
Rx DMA Error Bits.
  
  This field indicates the type of error that caused a Bus Error. For example, error response on the AXI interface.
  
  Bit 21
   - 1'b1: Error during data transfer by the Rx DMA
   - 1'b0: No error during data transfer by the Rx DMA
  Bit 20
   - 1'b1: Error during descriptor access
   - 1'b0: Error during data buffer access
  Bit 19
   - 1'b1: Error during read transfer
   - 1'b0: Error during write transfer
  This field is valid only when the FBE bit is set. This field does not generate an interrupt.
 RW 0x0
18:16 TEB 
Tx DMA Error Bits.
  
  This field indicates the type of error that caused a Bus Error. For example, error response on the AXI interface.
  
  Bit 18
   - 1'b1: Error during data transfer by the Tx DMA
   - 1'b0: No Error during data transfer by the Tx DMA
  Bit 17
   - 1'b1: Error during descriptor access
   - 1'b0: Error during data buffer access
  Bit 16
   - 1'b1: Error during read transfer
   - 1'b0: Error during write transfer
  This field is valid only when the FBE bit is set. This field does not generate an interrupt.
 RW 0x0
15 NIS 
Normal Interrupt Summary.
  
  Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH3_Interrupt_Enable register:
   - Bit 0: Transmit Interrupt
   - Bit 2: Transmit Buffer Unavailable
   - Bit 6: Receive Interrupt
  Only unmasked bits (interrupts for which interrupt enable is set in DMA_CH3_Interrupt_Enable register) affect the Normal Interrupt Summary bit.
  This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set is cleared.
 RW 0x0
14 AIS 
Abnormal Interrupt Summary.
  
  Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH3_Interrupt_Enable register:
   - Bit 1: Transmit Process Stopped
   - Bit 7: Receive Buffer Unavailable
   - Bit 8: Receive Process Stopped
   - Bit 9: Descriptor Definition Error
   - Bit 12: Fatal Bus Error
   - Bit 13: Context Descriptor Error
  Only unmasked bits affect the Abnormal Interrupt Summary bit.
  This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared.
 RW 0x0
13 CDE 
Context Descriptor Error.
  
  This bit indicates that the DMA Tx engine received a context descriptor in the middle of a packet (in an intermediate descriptor), and the DMA Tx engine ignored it.
 RW 0x0
12 FBE 
Fatal Bus Error.
  
  This bit indicates that a bus error occurred (as described in the EB field). When this bit is set, the corresponding DMA channel engine disables all bus accesses.
 RW 0x0
11:10 Reserved_11_10 
Reserved.
 RO 0x0
9 DDE 
Descriptor Definition Error.
  
  This bit indicates that a Descriptor Definition error occurred. When this bit is set, the corresponding DMA channel engine suspends Descriptor Fetch.
 RW 0x0
8 RPS 
Receive Process Stopped.
  
  This bit is asserted when the Rx process enters the Stopped state.
 RW 0x0
7 RBU 
Receive Buffer Unavailable.
  
  This bit indicates that the application owns the next descriptor in the Receive list, and the DMA cannot acquire it. The Rx process is suspended. To resume the Rx process, the application must change the ownership of the descriptor and advance the DMA_CH3_RxDesc_Tail_LPointer register. If this is not done, the RxDMA remains in SUSPEND state and results in overflow of the corresponding RxQueue.
 RW 0x0
6 RI 
Receive Interrupt.
  
  This bit indicates that the packet reception is complete. When packet reception is complete, Bit 31 of RDES1 is reset in the last descriptor, and the specific packet status information is updated in the descriptor.
  The reception remains in the Running state.
 RW 0x0
5:3 Reserved_5_3 
Reserved.
 RO 0x0
2 TBU 
Transmit Buffer Unavailable.
  
  This bit indicates that the application owns the next descriptor in the Transmit list, and the DMA cannot acquire it. Transmission is suspended. The TPS0 field of the DMA_Debug_Status3 register explains the Transmit Process state transitions.
  
  To resume the transmission, the application must do the following:
   - Change the ownership of the descriptor by setting Bit 31 of TDES0.
   - Issue a Transmit Poll Demand command by performing a write to the Transmit Descriptor Tail Pointer register.
 RW 0x0
1 TPS 
Transmit Process Stopped.
  
  This bit is set when the transmission is stopped.
 RW 0x0
0 TI 
Transmit Interrupt.
  
  This bit indicates that the packet transmission is complete. When transmission is complete, Bit 31 of TDES1 is reset in the first descriptor, and the specific packet status information is updated in the descriptor.
 RW 0x0