Hard Processor System (HPS) Address Map for the Agilex™ 5 SoC
This documentation is for the Agilex™ 5 SoC memory map.
Name | Start Address | End Address |
---|---|---|
OCRAM_memory |
|
|
SDMMC |
|
|
EMAC0 |
|
|
EMAC1 |
|
|
EMAC2 |
|
|
ECC |
|
|
OCRAM_registers |
|
|
PSI |
|
|
USBOTG |
|
|
NAND |
|
|
COMBOPHY |
|
|
UART |
|
|
I2C |
|
|
SPTIMER |
|
|
GPIO |
|
|
OSCTIMER |
|
|
Watchdog_timer |
|
|
Clock_Mgr |
|
|
Reset_Mgr |
|
|
System_Mgr |
|
|
Pin_Mux |
|
|
L4_NOC_FW |
|
|
L4_NOC_PRB |
|
|
I3C |
|
|
SPI |
|
|
DMAC0 |
|
|
DMAC1 |
|
|
USB3.1 |
|
|
SMMU_and_TCU |
|
|
MPFE_CSR |
|
|
CCU |
|
|
GIC |
|
|
LWHPS2FPGA_memory |
|
|
HPS2FPGA_memory |
|
|