rf_cmd_stat_regs Address Map

Module Instance Base Address End Address
i_nand__reg_apb__10b80000__rf_cmd_stat_regs__SEG_L4_MP_nand_s_0x0_0x10000 0x10B80000 0x10B8015F
Register Offset Width Access Reset Value Description
cmd_reg0 0x0 32 RW 0x00000000 
            Command register 0. Writing data to this register will initiate a new transaction of the NF controller.
            Command registers 0-3 are used to trigger controller operation.
            Fields encoding of those registers depends on selected work mode.
            Possible work modes are:
            1) CMD DMA work mode,
            2) PIO Mode,
            3) Generic Sequence Mode.
cmd_reg1 0x4 32 RW 0x00000000 
Command register 1.
cmd_reg2 0x8 32 RW 0x00000000 
Command register 2.
cmd_reg3 0xC 32 RW 0x00000000 
Command register 3.
cmd_status_ptr 0x10 32 RO 0x00000000 
Pointer register to select which thread status is selected.
cmd_status 0x14 32 RO 0x00000000 
Command status register for selected thread.
cmd_status_ext 0x18 32 RO 0x00000000 
Extended command status register for selected thread.
cmd_reg4 0x20 32 RW 0x00000000 
Command register 4.
cmd_reg5 0x24 32 RW 0x00000000 
Command register 5.
cmd_reg6 0x28 32 RW 0x00000000 
Command register 6.
intr_status 0x110 32 RO 0x00000000 
Controller status register
intr_enable 0x114 32 RW 0x00000000 
Interrupt enable register. If selected bit of this register is set, high logic value of the corresponding bit in intr_status will generate setting of external interrupt line.
ctrl_status 0x118 32 RO 0x00000000 
Controller internal state.
trd_status 0x120 32 RO 0x00000000 
Command Engine threads state.
trd_error_intr_status 0x128 32 RO 0x00000000 
Thread error indicates that the Command Engine thread detected an error condition. To get more information on the error, s/w needs to read the status field of the descriptor or appropriate status register depending on current work mode.
trd_error_intr_en 0x130 32 RO 0x00000000 
Interrupt enable register. If selected bit of this register is set, rising edge of corresponding bit in trd_error_intr_status will cause setting of the external interrupt line.
trd_comp_intr_status 0x138 32 RO 0x00000000 
Each bit of this field correspond to the Command Engine thread. Each bit informs about descriptor status for selected thread. It is set only when INT bit of descriptor is set
dma_target_error_l 0x140 32 RO 0x00000000 
DMA target error address [31:0]. This register can be used to obtain address of transaction which caused setting of cdma_terr or ddma_terr bits in the intr_status register.
dma_target_error_h 0x144 32 RO 0x00000000 
DMA target error address [63:32]. This register can be used to obtain address of transaction which caused setting of cdma_terr or ddma_terr bits in the intr_status register.
boot_status 0x148 32 RO 0x00000000 
This register provides status of the latest boot operation.
trd_timeout_intr_status 0x14C 32 RO 0x00000000 
Timeout status register indicates that a timeout condition on the Command Engine thread was detected.
trd_timeout_intr_en 0x154 32 RO 0x00000000 
Interrupt enable register. If selected bit of this register is set rising edge of corresponding bit in trd_timeout_intr_status will cause setting of the external interrupt line.