rf_cmd_stat_regs Summary

Base Address: 0x10B80000


Register Address Offset	Bit Fields
`i_nand__reg_apb__10b80000__rf_cmd_stat_regs__SEG_L4_MP_nand_s_0x0_0x10000`
`cmd_reg0` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`cmd0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`cmd0` `RW 0x0`
`cmd_reg1` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`cmd1` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`cmd1` `RW 0x0`
`cmd_reg2` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`cmd2` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`cmd2` `RW 0x0`
`cmd_reg3` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`cmd3` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`cmd3` `RW 0x0`
`cmd_status_ptr` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`													`thrd_status_sel` `RW 0x0`
`cmd_status` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`cmd_status` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`cmd_status` `RO 0x0`
`cmd_status_ext` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`cmd_status_ext` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`cmd_status_ext` `RO 0x0`
`cmd_reg4` `0x32` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`cmd4` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`cmd4` `RW 0x0`
`cmd_reg5` `0x36` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`cmd5` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`cmd5` `RW 0x0`
`cmd_reg6` `0x40` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`cmd6` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`cmd6` `RW 0x0`
`intr_status` `0x272` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_10` `RO 0x0`						`prot_err` `RW 0x0`	`di_ctx_err` `RW 0x0`	`Reserved`	`sdma_err` `RW 0x0`	`sdma_trigg` `RW 0x0`	`cmd_ignored` `RW 0x0`	`cmd_reg_par_err` `RW 0x0`	`ddma_terr` `RW 0x0`	`cdma_terr` `RW 0x0`	`cdma_idle` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_0` `RO 0x0`
`intr_enable` `0x276` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`intr_en` `RW 0x0`	`Reserved_10` `RO 0x0`					`prot_err_en` `RW 0x0`	`di_ctx_err_en` `RW 0x0`	`Reserved`	`sdma_err_en` `RW 0x0`	`sdma_trigg_en` `RW 0x0`	`cmd_ignored_en` `RW 0x0`	`cmd_reg_par_err_en` `RW 0x0`	`ddma_terr_en` `RW 0x0`	`cdma_terr_en` `RW 0x0`	`cdma_idle_en` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_0` `RO 0x0`
`ctrl_status` `0x280` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`															`sdma_paused` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_8` `RO 0x0`					`init_fail` `RO 0x0`	`init_comp` `RO 0x0`	`ctrl_busy` `RO 0x0`	`Reserved_5` `RO 0x0`			`Reserved`	`mc_busy` `RO 0x0`	`cmd_eng_busy` `RO 0x0`	`mdma_busy` `RO 0x0`	`sdma_busy` `RO 0x0`
`trd_status` `0x288` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`trd_busy` `RO 0x0`
`trd_error_intr_status` `0x296` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_8` `RO 0x0`								`trd7_error_stat` `RW 0x0`	`trd6_error_stat` `RW 0x0`	`trd5_error_stat` `RW 0x0`	`trd4_error_stat` `RW 0x0`	`trd3_error_stat` `RW 0x0`	`trd2_error_stat` `RW 0x0`	`trd1_error_stat` `RW 0x0`	`trd0_error_stat` `RW 0x0`
`trd_error_intr_en` `0x304` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`trd_error_intr_en` `RW 0x0`
`trd_comp_intr_status` `0x312` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_8` `RO 0x0`								`trd7_comp` `RW 0x0`	`trd6_comp` `RW 0x0`	`trd5_comp` `RW 0x0`	`trd4_comp` `RW 0x0`	`trd3_comp` `RW 0x0`	`trd2_comp` `RW 0x0`	`trd1_comp` `RW 0x0`	`trd0_comp` `RW 0x0`
`dma_target_error_l` `0x320` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`target_err_l` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`target_err_l` `RO 0x0`
`dma_target_error_h` `0x324` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`target_err_h` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`target_err_h` `RO 0x0`
`boot_status` `0x328` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`ctx_err` `RO 0x0`	`di_err` `RO 0x0`	`tim_out_err` `RO 0x0`	`Reserved_4` `RO 0x0`	`cpy_id` `RO 0x0`		`phy_err` `RO 0x0`	`bus_err` `RO 0x0`	`bch_err_type` `RO 0x0`
`trd_timeout_intr_status` `0x332` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_8` `RO 0x0`								`trd7_timeout_stat` `RW 0x0`	`trd6_timeout_stat` `RW 0x0`	`trd5_timeout_stat` `RW 0x0`	`trd4_timeout_stat` `RW 0x0`	`trd3_timeout_stat` `RW 0x0`	`trd2_timeout_stat` `RW 0x0`	`trd1_timeout_stat` `RW 0x0`	`trd0_timeout_stat` `RW 0x0`
`trd_timeout_intr_en` `0x340` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`trd_timeout_intr_en` `RW 0x0`