hps2fpga_scr Summary

SOC2FPGA Security Control Registers (SCR)

Base Address: 0x10D21200


Register Address Offset	Bit Fields
`noc_fw_soc2fpga__ocp_slv__10d21200__soc2fpga_scr`
`soc2fpga` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_14` `RO 0x0`				`sdm_nand` `RW 0x0`	`sdm_sdmmc` `RW 0x0`	`etr` `RW 0x0`	`axi_ap` `RW 0x0`	`nand` `RW 0x0`	`sdmmc` `RW 0x0`	`usb1` `RW 0x0`	`usb0` `RW 0x0`	`emac2` `RW 0x0`	`emac1` `RW 0x0`	`emac0` `RW 0x0`	`Reserved_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dmam0` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`