fpga2sdram_manager Address Map


Module Instance	Base Address	End Address
`soc_mpfe_noc_inst_0__mpfe_csr__18000000__fpga2sdram_manager_main_SidebandManager`	`0x18001000`	`0x180010FF`


Register	Offset	Width	Access	Reset Value	Description
`fpga2sdram_manager_main_SidebandManager_Id_CoreId`	`0x0`	`32`	`RO`	`0x7FF5AD0B`	Stores the Core Id and its checksum.
`fpga2sdram_manager_main_SidebandManager_Id_RevisionId`	`0x4`	`32`	`RO`	`0x4F9C1B00`	Stores a user-defined Id and the software revision.
`fpga2sdram_manager_main_SidebandManager_FaultEn`	`0x8`	`32`	`RO`	`0x00000000`	Register FaultEn
`fpga2sdram_manager_main_SidebandManager_FaultStatus`	`0xC`	`32`	`RO`	`0x00000000`	Register FaultStatus
`fpga2sdram_manager_main_SidebandManager_FlagInEn0`	`0x10`	`32`	`RO`	`0x00000000`	Register FlagInEn0
`fpga2sdram_manager_main_SidebandManager_FlagInStatus0`	`0x14`	`32`	`RO`	`0x00000000`	Register FlagInStatus0
`fpga2sdram_manager_main_SidebandManager_FlagOutSet0`	`0x50`	`32`	`RO`	`0x00000000`	Register FlagOutSet0
`fpga2sdram_manager_main_SidebandManager_FlagOutClr0`	`0x54`	`32`	`RO`	`0x00000000`	Register FlagOutClr0
`fpga2sdram_manager_main_SidebandManager_FlagOutStatus0`	`0x58`	`32`	`RO`	`0x00000100`	Register FlagOutStatus0