fpga2sdram_manager Summary

Base Address: 0x18001000


Register Address Offset	Bit Fields
`soc_mpfe_noc_inst_0__mpfe_csr__18000000__fpga2sdram_manager_main_SidebandManager`
`fpga2sdram_manager_main_SidebandManager_Id_CoreId` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CORECHECKSUM` `RO 0x7FF5AD`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CORECHECKSUM` `RO 0x7FF5AD`								`CORETYPEID` `RO 0xB`
`fpga2sdram_manager_main_SidebandManager_Id_RevisionId` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`FLEXNOCID` `RO 0x4F9C1B`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`FLEXNOCID` `RO 0x4F9C1B`								`USERID` `RO 0x0`
`fpga2sdram_manager_main_SidebandManager_FaultEn` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`FAULTEN` `RW 0x0`
`fpga2sdram_manager_main_SidebandManager_FaultStatus` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`FAULTSTATUS` `RO 0x0`
`fpga2sdram_manager_main_SidebandManager_FlagInEn0` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`				`FLAGINEN0` `RW 0x0`
`fpga2sdram_manager_main_SidebandManager_FlagInStatus0` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`				`FLAGINSTATUS0` `RO 0x0`
`fpga2sdram_manager_main_SidebandManager_FlagOutSet0` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`							`FLAGOUTSET0` `WO 0x0`
`fpga2sdram_manager_main_SidebandManager_FlagOutClr0` `0x84` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`							`FLAGOUTCLR0` `WO 0x0`
`fpga2sdram_manager_main_SidebandManager_FlagOutStatus0` `0x88` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`							`FLAGOUTSTATUS0` `RO 0x100`