UART1 Address Map
Module Instance | Base Address | End Address |
---|---|---|
i_uart_1__uart_csr__10c02100__uart_address_block__SEG_L4_SP_uart1_0x0_0x100
|
0x10C02100
|
0x10C021FF
|
Register | Offset | Width | Access | Reset Value | Description |
---|---|---|---|---|---|
RBR
|
0x0
|
32
|
RO
|
0x00000000
|
Receive Buffer Register |
IER
|
0x4
|
32
|
RW
|
0x00000000
|
Interrupt Enable Register |
IIR
|
0x8
|
32
|
RO
|
0x00000001
|
Interrupt Identification Register |
LCR
|
0xC
|
32
|
RW
|
0x00000000
|
Line Control Register |
MCR
|
0x10
|
32
|
RW
|
0x00000000
|
Modem Control Register |
LSR
|
0x14
|
32
|
RO
|
0x00000060
|
Line Status Register |
MSR
|
0x18
|
32
|
RO
|
0x00000000
|
Modem Status Register |
SCR
|
0x1C
|
32
|
RW
|
0x00000000
|
Scratchpad Register |
SRBR0
|
0x30
|
32
|
RO
|
0x00000000
|
Shadow Receive Buffer Register |
SRBR1
|
0x34
|
32
|
RO
|
0x00000000
|
Shadow Receive Buffer Register 1 |
SRBR2
|
0x38
|
32
|
RO
|
0x00000000
|
Shadow Receive Buffer Register 2 |
SRBR3
|
0x3C
|
32
|
RO
|
0x00000000
|
Shadow Receive Buffer Register 3 |
SRBR4
|
0x40
|
32
|
RO
|
0x00000000
|
Shadow Receive Buffer Register 4 |
SRBR5
|
0x44
|
32
|
RO
|
0x00000000
|
Shadow Receive Buffer Register 5 |
SRBR6
|
0x48
|
32
|
RO
|
0x00000000
|
Shadow Receive Buffer Register 6 |
SRBR7
|
0x4C
|
32
|
RO
|
0x00000000
|
Shadow Receive Buffer Register 7 |
SRBR8
|
0x50
|
32
|
RO
|
0x00000000
|
Shadow Receive Buffer Register 8 |
SRBR9
|
0x54
|
32
|
RO
|
0x00000000
|
Shadow Receive Buffer Register 9 |
SRBR10
|
0x58
|
32
|
RO
|
0x00000000
|
Shadow Receive Buffer Register 10 |
SRBR11
|
0x5C
|
32
|
RO
|
0x00000000
|
Shadow Receive Buffer Register 11 |
SRBR12
|
0x60
|
32
|
RO
|
0x00000000
|
Shadow Receive Buffer Register 12 |
SRBR13
|
0x64
|
32
|
RO
|
0x00000000
|
Shadow Receive Buffer Register 13 |
SRBR14
|
0x68
|
32
|
RO
|
0x00000000
|
Shadow Receive Buffer Register 14 |
SRBR15
|
0x6C
|
32
|
RO
|
0x00000000
|
Shadow Receive Buffer Register 15 |
FAR
|
0x70
|
32
|
RW
|
0x00000000
|
FIFO Access Register |
TFR
|
0x74
|
32
|
RO
|
0x00000000
|
Transmit FIFO Read |
RFW
|
0x78
|
32
|
RW
|
0x00000000
|
Receive FIFO Write |
USR
|
0x7C
|
32
|
RO
|
0x00000006
|
UART Status register |
TFL
|
0x80
|
32
|
RO
|
0x00000000
|
Transmit FIFO Level |
RFL
|
0x84
|
32
|
RO
|
0x00000000
|
Receive FIFO Level |
SRR
|
0x88
|
32
|
RW
|
0x00000000
|
Software Reset Register |
SRTS
|
0x8C
|
32
|
RW
|
0x00000000
|
Shadow Request to Send |
SBCR
|
0x90
|
32
|
RW
|
0x00000000
|
Shadow Break Control Register |
SDMAM
|
0x94
|
32
|
RW
|
0x00000000
|
Shadow DMA Mode |
SFE
|
0x98
|
32
|
RW
|
0x00000000
|
Shadow FIFO Enable |
SRT
|
0x9C
|
32
|
RW
|
0x00000000
|
Shadow RCVR Trigger |
STET
|
0xA0
|
32
|
RW
|
0x00000000
|
Shadow TX Empty Trigger |
HTX
|
0xA4
|
32
|
RW
|
0x00000000
|
Halt TX |
DMASA
|
0xA8
|
32
|
RW
|
0x00000000
|
DMA Software Acknowledge |
CPR
|
0xF4
|
32
|
RO
|
0x00083F32
|
Component Parameter Register |
UCV
|
0xF8
|
32
|
RO
|
0x3331352A
|
Component Version |
CTR
|
0xFC
|
32
|
RO
|
0x44570110
|
Component Type Register |