NAND_dataslice_Rfile Summary

Base Address: 0x10B82000


Register Address Offset	Bit Fields
`i_nand__reg_apb__10b80000__dataslice_Rfile__SEG_L4_MP_nand_s_0x0_0x10000`
`phy_dq_timing_reg` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`io_mask_always_on` `RW 0x1`	`Reserved_7` `RO 0x0`	`io_mask_end` `RW 0x0`			`io_mask_start` `RW 0x0`			`data_clkperiod_delay` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`data_select_tsel_start` `RW 0x0`				`data_select_tsel_end` `RW 0x0`				`Reserved_2` `RO 0x0`	`data_select_oe_start` `RW 0x0`			`Reserved_1` `RO 0x0`	`data_select_oe_end` `RW 0x2`
`phy_dqs_timing_reg` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_10` `RO 0x0`								`dqs_clkperiod_delay` `RW 0x0`	`use_ext_lpbk_dqs` `RW 0x0`	`use_lpbk_dqs` `RW 0x0`	`use_phony_dqs` `RW 0x1`	`use_phony_dqs_cmd` `RW 0x1`	`Reserved_5` `RO 0x0`		`phony_dqs_sel` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`dqs_select_tsel_start` `RW 0x0`				`dqs_select_tsel_end` `RW 0x0`				`dqs_select_oe_start` `RW 0x0`				`dqs_select_oe_end` `RW 0x4`
`phy_gate_lpbk_ctrl_reg` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`sync_method` `RW 0x0`	`sw_dqs_phase_bypass` `RW 0x0`	`en_sw_half_cycle` `RW 0x0`	`sw_half_cycle_shift` `RW 0x0`	`param_phase_detect_sel_oe` `RW 0x0`			`rd_del_sel` `RW 0x34`						`underrun_suppress` `RW 0x0`	`Reserved_9` `RO 0x0`	`rd_del_sel_empty` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`lpbk_err_check_timing` `RW 0x0`			`lpbk_fail_muxsel` `RW 0x0`	`loopback_control` `RW 0x0`		`lpbk_internal` `RW 0x0`	`lpbk_en` `RW 0x0`	`Reserved_3` `RO 0x0`	`gate_cfg_always_on` `RW 0x0`	`gate_cfg_close` `RW 0x0`		`gate_cfg` `RW 0x0`
`phy_dll_master_ctrl_reg` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`								`param_dll_bypass_mode` `RW 0x1`	`param_phase_detect_sel` `RW 0x0`			`Reserved_2` `RO 0x0`	`param_dll_lock_num` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`param_dll_start_point` `RW 0x0`
`phy_dll_slave_ctrl_reg` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`read_dqs_cmd_delay` `RW 0x0`								`clk_wrdqs_delay` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`clk_wr_delay` `RW 0x0`								`read_dqs_delay` `RW 0x0`
`phy_ie_timing_reg` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_6` `RO 0x0`											`ie_always_on` `RW 0x1`	`Reserved_5` `RO 0x0`	`dq_ie_start` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`dq_ie_stop` `RW 0x0`			`Reserved_3` `RO 0x0`	`dqs_ie_start` `RW 0x0`			`Reserved_2` `RO 0x0`	`dqs_ie_stop` `RW 0x0`			`rddata_en_ie_dly` `RW 0x0`
`phy_obs_reg_0` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_6` `RO 0x0`				`dqs_cmd_overflow` `RO 0x0`	`dqs_cmd_underrun` `RO 0x0`	`dqs_overflow` `RO 0x0`	`dqs_underrun` `RO 0x0`	`lpbk_dq_data` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`lpbk_dq_data` `RO 0x0`								`Reserved_1` `RO 0x0`						`lpbk_status` `RO 0x0`
`phy_dll_obs_reg_0` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`lock_inc_dbg` `RO 0x0`								`lock_dec_dbg` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`dll_lock_value` `RO 0x0`								`dll_unlock_cnt` `RO 0x0`					`dll_locked_mode` `RO 0x0`		`dll_lock` `RO 0x0`
`phy_dll_obs_reg_1` `0x32` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`								`decoder_out_wr` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`decoder_out_rd_cmd` `RO 0x0`								`decoder_out_rd` `RO 0x0`
`phy_dll_obs_reg_2` `0x36` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`decoder_out_wrdqs` `RO 0x0`
`phy_static_togg_reg` `0x40` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`							`read_dqs_togg_enable` `RW 0x0`	`static_togg_enable` `RW 0x0`				`Reserved_2` `RO 0x0`			`static_togg_global_enable` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`static_tog_clk_div` `RW 0x0`
`phy_wr_deskew_reg` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`wr_dq7_deskew_delay` `RW 0x0`				`wr_dq6_deskew_delay` `RW 0x0`				`wr_dq5_deskew_delay` `RW 0x0`				`wr_dq4_deskew_delay` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`wr_dq3_deskew_delay` `RW 0x0`				`wr_dq2_deskew_delay` `RW 0x0`				`wr_dq1_deskew_delay` `RW 0x0`				`wr_dq0_deskew_delay` `RW 0x0`
`phy_wr_rd_deskew_cmd_reg` `0x48` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`				`rd_cmd_deskew_delay` `RW 0x0`				`Reserved_6` `RO 0x0`							`cmd_clkperiod_delay` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_5` `RO 0x0`	`cmd_sw_dq_phase_bypass` `RW 0x0`	`cmd_en_sw_half_cycle` `RW 0x0`	`cmd_sw_half_cycle_shift` `RW 0x0`	`Reserved_2` `RO 0x0`	`cmd_phase_detect_sel` `RW 0x0`			`Reserved_1` `RO 0x0`				`wr_cmd_deskew_delay` `RW 0x0`
`phy_wr_deskew_pd_ctrl_0_reg` `0x52` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_16` `RO 0x0`	`dq3_sw_dq_phase_bypass` `RW 0x0`	`dq3_en_sw_half_cycle` `RW 0x0`	`dq3_sw_half_cycle_shift` `RW 0x0`	`Reserved_13` `RO 0x0`	`dq3_phase_detect_sel` `RW 0x0`			`Reserved_12` `RO 0x0`	`dq2_sw_dq_phase_bypass` `RW 0x0`	`dq2_en_sw_half_cycle` `RW 0x0`	`dq2_sw_half_cycle_shift` `RW 0x0`	`Reserved_9` `RO 0x0`	`dq2_phase_detect_sel` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_8` `RO 0x0`	`dq1_sw_dq_phase_bypass` `RW 0x0`	`dq1_en_sw_half_cycle` `RW 0x0`	`dq1_sw_half_cycle_shift` `RW 0x0`	`Reserved_5` `RO 0x0`	`dq1_phase_detect_sel` `RW 0x0`			`Reserved_4` `RO 0x0`	`dq0_sw_dq_phase_bypass` `RW 0x0`	`dq0_en_sw_half_cycle` `RW 0x0`	`dq0_sw_half_cycle_shift` `RW 0x0`	`Reserved_1` `RO 0x0`	`dq0_phase_detect_sel` `RW 0x0`
`phy_wr_deskew_pd_ctrl_1_reg` `0x56` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_16` `RO 0x0`	`dq7_sw_dq_phase_bypass` `RW 0x0`	`dq7_en_sw_half_cycle` `RW 0x0`	`dq7_sw_half_cycle_shift` `RW 0x0`	`Reserved_13` `RO 0x0`	`dq7_phase_detect_sel` `RW 0x0`			`Reserved_12` `RO 0x0`	`dq6_sw_dq_phase_bypass` `RW 0x0`	`dq6_en_sw_half_cycle` `RW 0x0`	`dq6_sw_half_cycle_shift` `RW 0x0`	`Reserved_9` `RO 0x0`	`dq6_phase_detect_sel` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_8` `RO 0x0`	`dq5_sw_dq_phase_bypass` `RW 0x0`	`dq5_en_sw_half_cycle` `RW 0x0`	`dq5_sw_half_cycle_shift` `RW 0x0`	`Reserved_5` `RO 0x0`	`dq5_phase_detect_sel` `RW 0x0`			`Reserved_4` `RO 0x0`	`dq4_sw_dq_phase_bypass` `RW 0x0`	`dq4_en_sw_half_cycle` `RW 0x0`	`dq4_sw_half_cycle_shift` `RW 0x0`	`Reserved_1` `RO 0x0`	`dq4_phase_detect_sel` `RW 0x0`
`phy_rd_deskew_reg` `0x60` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rd_dq7_deskew_delay` `RW 0x0`				`rd_dq6_deskew_delay` `RW 0x0`				`rd_dq5_deskew_delay` `RW 0x0`				`rd_dq4_deskew_delay` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rd_dq3_deskew_delay` `RW 0x0`				`rd_dq2_deskew_delay` `RW 0x0`				`rd_dq1_deskew_delay` `RW 0x0`				`rd_dq0_deskew_delay` `RW 0x0`
`phy_version_reg` `0x112` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`combo_phy_magic_number` `RO 0x6182`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`phy_fix` `RO 0x1`								`phy_rev` `RO 0x7`
`phy_features_reg` `0x116` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_15` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`asf_sup` `RO 0x0`	`pll_sup` `RO 0x0`	`jtag_sup` `RO 0x0`	`ext_lpbk_dqs` `RO 0x1`	`reg_intf` `RO 0x1`	`per_bit_deskew` `RO 0x1`	`dfi_clock_ratio` `RO 0x1`	`aging` `RO 0x1`	`dll_tap_num` `RO 0x1`	`bank_num` `RO 0x3`		`sd_emmc` `RO 0x1`	`Reserved`	`sdr_16bit` `RO 0x1`	`Reserved`	`Reserved`