MPFE_SCR Summary

MPFE Security Control Registers (SCR)

Base Address: 0x18000D00


Register Address Offset	Bit Fields
`soc_noc_fw_mpfe_csr_inst_0__fw_mpfe_csr__18000d00__mpfe_scr__MPFE_SCR`
`IO96B0_reg` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`															`axi_ap` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`IO96B1_reg` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`															`axi_ap` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`noc_csr` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`															`axi_ap` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`