DWC_usb31_block_eXtensible_Host_Cntrl_Cap_Regs Address Map

USB 3.1 eXtensible Host Controller Capability Register Block
Module Instance Base Address End Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_eXtensible_Host_Cntrl_Cap_Regs__SEG_L4_AHB_USB1_0x0_0x100000 0x11000000 0x1100001F
Register Offset Width Access Reset Value Description
CAPLENGTH 0x0 32 RO 0x01100020 
Capability Registers Length
  
  Host Controller Operational Registers = Base address + CAPLENGTH
  
  where CAPLENGTH is `DWC_USB31_HOST_CAP_REG_LEN whose default value is 20h.
HCSPARAMS1 0x4 32 RO 0x0200017F 
Structural Parameters 1 Register
  
  For register definitions, refer to the xHCI specification.
HCSPARAMS2 0x8 32 RO 0x140000F1 
Structural Parameters 2 Register
  
  For register definitions, refer to the xHCI specification.
HCSPARAMS3 0xC 32 RO 0x0200000A 
Structural Parameters 3 Register
  
  For register definitions, refer to the xHCI specification.
HCCPARAMS1 0x10 32 RO 0x0110FFCD 
Capability Parameters 1 Register
  
  For register definitions, refer to the xHCI specification.
DBOFF 0x14 32 RO 0x00002000 
Doorbell Offset Register
  
  For register definitions, refer to the xHCI specification.
  
  The value of this register is 8192.So the DoorBell Registers Start on a 4K Boundary.
  
  This value was changed in Release 1.80a_lp02 to make it alligned to a Page Boundary. Before the 1.80a_lp02 release, the value was not on a Page boundary.
RTSOFF 0x18 32 RO 0x00001000 
Runtime Register Space Offset Register
  
  Base address + 0x18
  
  where RTSOFF is `DWC_USB31_HC_RUNTIME_REGISTER_SPACE_OFFSET. This parameter is defined as 4096. So the Run time registers start on a fresh 4K Page. 
  
  This value was changed in Release 1.80a_lp02 to make it alligned to a Page Boundary. Before the 1.80a_lp02 release, the value was not on a Page boundary.
HCCPARAMS2 0x1C 32 RO 0x0000003F 
Host Controller Capability Parameters 2
  
  For register definitions, refer to the xHCI specification.