DWC_usb31_block_Host_Cntrl_Oper_Regs Address Map

USB3 Host Cntrl Oper Regs Block
Module Instance Base Address End Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_Host_Cntrl_Oper_Regs__SEG_L4_AHB_USB1_0x0_0x100000 0x11000020 0x1100041F
Register Offset Width Access Reset Value Description
USBCMD 0x0 32 RW 0x00000000 
USB Command Register
  
  For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.1.
USBSTS 0x4 32 RW 0x00000801 
USB Status Register Bit Definitions
  
  For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.1.
PAGESIZE 0x8 32 RO 0x00000001 
Page Size Register Bit Definitions
  
  Use this register to enable or disable the reporting of specific USB Device Notification Transaction Packets being received.
  
  A Notification Enable (Nx, where x = 0 to 15) flag is defined for each of the 16 possible device notification types. If a flag is set for a specific notification type, a Device Notification Event is generated when the respective notification packet is received. After reset, all notifications are disabled. Refer to section 6.4.2.7 of the Databookfor more information.
  
  This register is written as a Dword. Byte writes produce undefined results.
DNCTRL 0x14 32 RW 0x00000000 
Device Notification Register Bit Definitions
  
  For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.1.
CRCR_LO 0x18 32 RW 0x00000000 
CRCR_LO
  
  For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.1.
CRCR_HI 0x1C 32 RW 0x00000000 
CRCR_HI
DCBAAP_LO 0x30 32 RW 0x00000000 
DCBAAP_LO
DCBAAP_HI 0x34 32 RW 0x00000000 
DCBAAP_HI
  
  For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.1.
CONFIG 0x38 32 RW 0x00000000 
Configure Register Bit Definitions
  
   This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST). The initial conditions of a port are described in section 4.19 of the DWC Cores Enhanced SuperSpeed USB 3.1 Controller Databook.