DMAC0_Channel2 Address Map

DW_axi_dmac Channel 2 register address block


Module Instance	Base Address	End Address
`i_dma__dmac0_ahb_slv__10db0000__Channel2_Registers_Address_Block__SEG_L4_AHB_dmac0_s_0x0_0x10000`	`0x10DB0200`	`0x10DB029F`


Register	Offset	Width	Access	Reset Value	Description
`CH2_SAR`	`0x0`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel $i Source Address Register
`CH2_DAR`	`0x8`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel $i Destination Address Register
`CH2_BLOCK_TS`	`0x10`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel $i Block Transfer Size Register
`CH2_CTL`	`0x18`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel $i Control Register
`CH2_CFG2`	`0x20`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel $i Configuration Register 2
`CH2_LLP`	`0x28`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel $i Linked List Pointer Register
`CH2_STATUSREG`	`0x30`	`64`	`RO`	`0x0000000000000000`	DW_axi_dmac Channel $i Status Register
`CH2_SWHSSRCREG`	`0x38`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel $i Software Handshake Source Register
`CH2_SWHSDSTREG`	`0x40`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel $i Software Handshake Destination Register
`CH2_BLK_TFR_RESUMEREQREG`	`0x48`	`64`	`WO`	`0x0000000000000000`	DW_axi_dmac Channel $i Block Transfer Resume Request Register
`CH2_AXI_IDREG`	`0x50`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel $i AXI ID Register
`CH2_AXI_QOSREG`	`0x58`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel $i AXI QoS Register
`CH2_INTSTATUS_ENABLEREG`	`0x80`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel $i Interrupt Status Enable Register
`CH2_INTSTATUS`	`0x88`	`64`	`RO`	`0x0000000000000000`	DW_axi_dmac Channel $i Interrupt Status Register
`CH2_INTSIGNAL_ENABLEREG`	`0x90`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel $i Interrupt Signal Enable Register
`CH2_INTCLEARREG`	`0x98`	`64`	`WO`	`0x0000000000000000`	DW_axi_dmac Channel $i Interrupt Status Clear Register