COMBOPHY_dataslice_Rfile Address Map


Module Instance	Base Address	End Address
`i_combo_phy__combophy_reg_apb__10b92000__dataslice_Rfile__SEG_L4_MP_combophy_0x0_0x10000`	`0x10B92000`	`0x10B92077`


Register	Offset	Width	Access	Reset Value	Description
`phy_dq_timing_reg`	`0x0`	`32`	`RW`	`0x80000002`	This register controls the DQ related timing.
`phy_dqs_timing_reg`	`0x4`	`32`	`RO`	`0x00180004`	This register controls the DQS related timing.
`phy_gate_lpbk_ctrl_reg`	`0x8`	`32`	`RW`	`0x01A00000`	This register controls the gate and loopback control related timing.
`phy_dll_master_ctrl_reg`	`0xC`	`32`	`RO`	`0x00800000`	This register holds the control for the Master DLL logic.
`phy_dll_slave_ctrl_reg`	`0x10`	`32`	`RW`	`0x00000000`	This register holds the control for the slave DLL logic.
`phy_ie_timing_reg`	`0x14`	`32`	`RO`	`0x00100000`	This register controls the DQS related timing.
`phy_obs_reg_0`	`0x18`	`32`	`RO`	`0x00000000`	This register holds the following observable points in the PHY.
`phy_dll_obs_reg_0`	`0x1C`	`32`	`RO`	`0x00000000`	This register holds the following observable points in the PHY.
`phy_dll_obs_reg_1`	`0x20`	`32`	`RO`	`0x00000000`	This register holds the following observable points in the PHY.
`phy_dll_obs_reg_2`	`0x24`	`32`	`RO`	`0x00000000`	This register holds the following observable points in the PHY.
`phy_static_togg_reg`	`0x28`	`32`	`RO`	`0x00000000`	This register controls the static aging feature of the PHY.
`phy_wr_deskew_reg`	`0x2C`	`32`	`RW`	`0x00000000`	This register holds the values of delay of each DQ bit on the write path.
`phy_wr_rd_deskew_cmd_reg`	`0x30`	`32`	`RO`	`0x00000000`	This register holds the values of delay of CMD bit on the write and read path as well as the values of phase detect block for CMD bit on the write path.
`phy_wr_deskew_pd_ctrl_0_reg`	`0x34`	`32`	`RO`	`0x00000000`	This register holds the values of phase detect block for each DQ bit on the write path.
`phy_wr_deskew_pd_ctrl_1_reg`	`0x38`	`32`	`RO`	`0x00000000`	This register holds the values of phase detect block for each DQ bit on the write path.
`phy_rd_deskew_reg`	`0x3C`	`32`	`RW`	`0x00000000`	This register holds the values of delay of each DQ bit on the read path.
`phy_version_reg`	`0x70`	`32`	`RO`	`0x61820107`	This register contains release identification number.
`phy_features_reg`	`0x74`	`32`	`RO`	`0x00001FFF`	This register shows available hardware features.