CCU_IOS Summary

Base Address: 0x1C009000


Register Address Offset	Bit Fields
`i_ccu__DSU__1c000000__CCU_IOS`
`DIIUIDR` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RO 0x1`	`Rsvd1` `RO 0x0`							`NUnitId` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NUnitId` `RO 0x0`				`NRRI` `RO 0x0`				`RPN` `RO 0x9`
`DIIUFUIDR` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`FUnitId` `RO 0x9`
`DIIUTAR` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`															`TransActv` `RO 0x0`
`DIIUUEDR` `0x280` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`														`TransErrDetEn` `RW 0x0`	`ProtErrDetEn` `RW 0x0`
`DIIUUEIR` `0x284` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd1` `RO 0x0`														`TransErrIntEn` `RW 0x0`	`ProtErrIntEn` `RW 0x0`
`DIIUUESR` `0x288` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrInfo` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`								`ErrType` `RO 0x0`				`Rsvd1` `RO 0x0`			`ErrVld` `RW 0x0`
`DIIUUELR0` `0x292` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrWord` `RW 0x0`						`ErrWay` `RW 0x0`						`ErrEntry` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrEntry` `RW 0x0`
`DIIUUELR1` `0x296` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`												`ErrAddr` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ErrAddr` `RW 0x0`
`DIIUUESAR` `0x300` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ErrInfo` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd2` `RO 0x0`								`ErrType` `RW 0x0`				`Rsvd1` `RO 0x0`			`ErrVld` `RW 0x0`
`DIICCTRLR` `0x2304` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`inc` `RW 0x100`												`gain` `RW 0x2`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Rsvd` `RO 0x0`								`dn0Rx` `RW 0x0`	`dn0Tx` `RW 0x0`	`ndn2Rx` `RW 0x0`	`ndn2Tx` `RW 0x0`	`ndn1Rx` `RW 0x0`	`ndn1Tx` `RW 0x0`	`ndn0Rx` `RW 0x0`	`ndn0Tx` `RW 0x0`
`DIICNTCR0` `0x2816` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`		`CntEvtFirst` `RW 0x0`						`Rsvd0` `RO 0x0`		`CntEvtSecond` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MinStallPeriod` `RW 0x0`			`FilterSel` `RW 0x0`			`SSRCount` `RW 0x0`			`CounterCtl` `RW 0x0`			`OverFlowStatus` `RO 0x0`	`InterruptEn` `RW 0x0`	`CountClr` `RW 0x0`	`CountEn` `RW 0x0`
`DIICNTVR0` `0x2820` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountVal` `RW 0x0`
`DIICNTSR0` `0x2824` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountSatVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountSatVal` `RW 0x0`
`DIICNTCR1` `0x2832` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`		`CntEvtFirst` `RW 0x0`						`Rsvd0` `RO 0x0`		`CntEvtSecond` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MinStallPeriod` `RW 0x0`			`FilterSel` `RW 0x0`			`SSRCount` `RW 0x0`			`CounterCtl` `RW 0x0`			`OverFlowStatus` `RO 0x0`	`InterruptEn` `RW 0x0`	`CountClr` `RW 0x0`	`CountEn` `RW 0x0`
`DIICNTVR1` `0x2836` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountVal` `RW 0x0`
`DIICNTSR1` `0x2840` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountSatVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountSatVal` `RW 0x0`
`DIICNTCR2` `0x2848` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`		`CntEvtFirst` `RW 0x0`						`Rsvd0` `RO 0x0`		`CntEvtSecond` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MinStallPeriod` `RW 0x0`			`FilterSel` `RW 0x0`			`SSRCount` `RW 0x0`			`CounterCtl` `RW 0x0`			`OverFlowStatus` `RO 0x0`	`InterruptEn` `RW 0x0`	`CountClr` `RW 0x0`	`CountEn` `RW 0x0`
`DIICNTVR2` `0x2852` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountVal` `RW 0x0`
`DIICNTSR2` `0x2856` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountSatVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountSatVal` `RW 0x0`
`DIICNTCR3` `0x2864` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Rsvd1` `RO 0x0`		`CntEvtFirst` `RW 0x0`						`Rsvd0` `RO 0x0`		`CntEvtSecond` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MinStallPeriod` `RW 0x0`			`FilterSel` `RW 0x0`			`SSRCount` `RW 0x0`			`CounterCtl` `RW 0x0`			`OverFlowStatus` `RO 0x0`	`InterruptEn` `RW 0x0`	`CountClr` `RW 0x0`	`CountEn` `RW 0x0`
`DIICNTVR3` `0x2868` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountVal` `RW 0x0`
`DIICNTSR3` `0x2872` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CountSatVal` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CountSatVal` `RW 0x0`
`DIIUUEVIR` `0x4084` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`EngVerId` `RO 0xB92A000B`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`EngVerId` `RO 0xB92A000B`
`DIIUINFOR` `0x4092` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Valid` `RO 0x1`	`Rsvd1` `RO 0x0`											`UST` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UT` `RO 0xA`				`ImplVer` `RO 0x323`