2EMAC2_DWCXG_MTL Address Map

Mac Transaction Layer (MTL) Common/General Registers.
Module Instance Base Address End Address
u_emac2__apb_reg_config_slave__10830000__DWCXG_MTL__SEG_L4_MP_emac2_s_0x0_0x10000 0x10831000 0x108310FF
Register Offset Width Access Reset Value Description
MTL_Operation_Mode 0x0 32 RW 0x00000000 
The Operation Mode register establishes the Transmit and Receive operating modes and commands.
MTL_Debug_Control 0x8 32 RW 0x00000000 
The FIFO Debug Access Control and Status register controls the operation mode of FIFO debug access.
  
  Note: Consecutive write or read to this register must be performed after at least 16 clock cycles of the slowest clock among MAC Transmitter/Receiver clock and Application/CSR clock.
MTL_Debug_Status 0xC 32 RW 0x00000018 
The FIFO Debug Status register contains the status of FIFO debug access.
  
  Note:  Consecutive write or read to this register must be performed after at least 16 clock cycles of the slowest clock among MAC Transmitter/Receiver clock and Application/CSR clock.
MTL_FIFO_Debug_Data 0x10 32 RW 0x00000000 
The FIFO Debug Data register contains the data to be written to or read from the FIFOs.
  
  Note:  Consecutive write or read to this register must be performed after at least 16 clock cycles of the slowest clock among MAC Transmitter/Receiver clock and Application/CSR clock.
MTL_Interrupt_Status 0x20 32 RO 0x00000000 
The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC.
MTL_RxQ_DMA_Map0 0x30 32 RW 0x00000000 
The Receive Queue and DMA Channel Mapping 0 register controls the static or dynamic mapping of Receive Queues 0-3 to Receive DMA Channels.
MTL_RxQ_DMA_Map1 0x34 32 RW 0x00000000 
The Receive Queue and DMA Channel Mapping 1 register controls the static or dynamic mapping of Receive Queues 4-7 to Receive DMA Channels.
MTL_TC_Prty_Map0 0x40 32 RW 0x00000000 
This register contains the priority values assigned to traffic classes 0 to 3.
MTL_TC_Prty_Map1 0x44 32 RW 0x00000000 
This register contains the priority values assigned to traffic classes 4 to 7.
MTL_TBS_CTRL 0x48 32 RW 0x00000000 
This register controls the operation of Time Based Scheduling.
MTL_TBS_STATS 0x4C 32 RW 0x00000000 
This register provides the One Hot encoded Queue numbers that have the frame drop related error
MTL_EST_Control 0x50 32 RW 0x00000000 
This register controls the operation of Enhancements to Scheduled Transmission (IEEE 802.1Qbv).
MTL_EST_Overhead 0x54 32 RW 0x00000000 
This register indicates the value of Overhead.
MTL_EST_Status 0x58 32 RW 0x00000000 
This register provides Status related to Enhancements to Scheduled Transmission (IEEE 802.1Qbv).
MTL_EST_Sch_Error 0x60 32 RW 0x00000000 
This register provides the One Hot encoded Queue numbers that have the scheduling related error (timeout).
MTL_EST_Frm_Size_Error 0x64 32 RW 0x00000000 
This register provides the One Hot encoded Queue numbers that have the Frame Size related error.
MTL_EST_Frm_Size_Capture 0x68 32 RO 0x00000000 
This register captures the Frame Size and Queue Number of the first occurrence of the Frame Size related error. Upon clearing, this register captures the data of the next occurrence of a similar error.
MTL_EST_Intr_Enable 0x70 32 RW 0x00000000 
This register implements the Interrupt Enable bits for the various events that generate an interrupt. Bit positions have a 1- to-1 correspondence with the status bit positions in MTL_EST_Status register.
MTL_GCL_Control 0x80 32 RW 0x00000000 
This register provides the control information for reading/writing to the Gate Control lists.
MTL_GCL_Data 0x84 32 RW 0x00000000 
This register holds the read data or write data in case of reads and writes respectively.
MTL_FPE_CTRL_STS 0x90 32 RW 0x00000000 
This register controls the operation of, and provides status for Frame Preemption (IEEE 802.1Qbu/802.3br).
MTL_FPE_Advance 0x94 32 RW 0x00000000 
This register holds the Hold and Release Advance time.