2EMAC2_DWCXG_DMA_CH2 Address Map

The DMA Channel2 Control register specifies the MSS value for segmentation, length to skip between two descriptors, and also the features such as header splitting and 8xPBL mode.

The DMA Channel2 Transmit Control register controls the Tx features such as PBL, TCP segmentation, and Tx Channel weights.

The DMA Channel2 Receive Control register controls the Rx features such as PBL, buffer size, and extended status.

This register contains the control bits for slot function and its status for Transmit path.

The Channel2 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode.
  
  
  You can write to this register only when the Tx DMA has stopped, that is, the ST bit is set to zero in DMA_CH2_Tx_Control register. When stopped, this register can be written with a new descriptor list address. When you set the ST bit to 1, the DMA takes the newly-programmed descriptor base address. If this register is not changed when the ST bit is set to 0, the DMA takes the descriptor address where it was stopped earlier. This register must be programmed with desired higher address before programming the DMA_CH2_TxDesc_List_LAddress register.

The Channel2 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword, or Lword-aligned (for 64-bit or 128-bit data bus). The DMA internally converts it to bus width aligned address by making the corresponding LSB to low.
  
  
  You can write to this register only when the Tx DMA has stopped, that is, the ST bit is set to zero in DMA_CH2_Tx_Control register. When stopped, this register can be written with a new descriptor list address. When you set the ST bit to 1, the DMA takes the newly-programmed descriptor base address. If this register is not changed when the ST bit is set to 0, the DMA takes the descriptor address where it was stopped earlier.

The Channel2 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode.
  
  
  You can write to this register only when the Rx DMA has stopped, that is, the SR bit is set to zero in DMA_CH2_Rx_Control register. When stopped, this register can be written with a new descriptor list address. When you set the SR bit to 1, the DMA takes the newly-programmed descriptor base address. If this register is not changed when the SR bit is set to 0, the DMA takes the descriptor address where it was stopped earlier. This register must be programmed with desired higher address before programming the DMA_CH2_RxDesc_List_LAddress register.

The Channel2 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list.
  
  This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory space of the application and must be Dword or Lword-aligned (for 64-bit or 128-bit data bus). The DMA internally converts it to bus width aligned address by making the corresponding LS bits low. Writing to this register is permitted only when reception is stopped. When stopped, this register must be written to before the receive Start command is given. You can write to this register only when Rx DMA has stopped, that is, SR bit is set to zero in DMA_CH2_Rx_Control register. When stopped, this register can be written with a new descriptor list address.
  
  When you set the SR bit to 1, the DMA takes the newly programmed descriptor base address.

The Channel2 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list.

The Channel2 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list.

The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring.

The Channel2 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring.

The Channel2 Interrupt Enable register enables the interrupts reported by the Status register.

The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of packets received (RBCT) based on the value of programmable bit PSEL. When either of these fields are written with a non-zero value, the interrupt timer is enabled when a packet transfer is completed for which RI is not generated. The timers are cleared when the RI is generated by that RxDMA channel.

The Channel2 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are equal to the value written in the DMA_CH2_TxDesc_List_HAddress. Therefore, the upper address bits are not given in the register map.

The Channel2 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to the value written in the DMA_CH2_RxDesc_List_HAddress. Therefore, the upper address bits are not given in the register map.

The Channel2 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode.

The Channel2 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA.

The Channel2 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode.

The Channel2 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA.

The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA.

DMA Channe2 Debug Status register

The DMA Channel0 Descriptor Cache Fill Level Status register.

This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH2_Rx_Control register.

This register indicates the Offset of the Tx Descriptor List, for which the DMA engine is fetching the data.

The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List, for which the DMA engine is transferring the data.

This register indicates the Offset of the Tx Descriptor List, for which the DMA engine is closing the descriptor.

This register indicates the Offset of the Rx Descriptor List, for which the DMA engine is closing the descriptor.