1EMAC1_DWCXG_MTL_TCQ1 Address Map

MTL Traffic Class/Queue (#i) Registers.
Module Instance Base Address End Address
u_emac1__apb_reg_config_slave__10820000__DWCXG_MTL_TCQ1__SEG_L4_MP_emac1_s_0x0_0x10000 0x10821180 0x108211FF
Register Offset Width Access Reset Value Description
MTL_TxQ1_Operation_Mode 0x0 32 RW 0x00000000 
The Queue 1 Transmit Operation Mode register establishes the Transmit queue operating modes and commands.
MTL_TxQ1_Underflow 0x4 32 RO 0x00000000 
The Queue 1 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow.
MTL_TxQ1_Debug 0x8 32 RO 0x00000000 
The Queue 1 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 1 and Traffic Class 0.
MTL_TC1_ETS_Control 0x10 32 RW 0x00000000 
This register configures the transmission selection algorithm, for Traffic Class 0.This register is not available in single traffic class configuration.
MTL_TC1_ETS_Status 0x14 32 RO 0x00000000 
This register contains the information of average bits transmitted over a slot interval of 10 million bit times, for Traffic Class 0.
MTL_TC1_Quantum_Weight 0x18 32 RW 0x00000000 
The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn, where n = 1 to 7, this register is not available when the number of traffic classes selected is less than n + 1
  
  This register is not available in corresponding Queues 8-15 registers..
MTL_RxQ1_Operation_Mode 0x40 32 RW 0x00000000 
The Queue 1 Receive Operation Mode register establishes the Receive queue operating modes and command.
MTL_RxQ1_Missed_Pkt_Overflow_Cnt 0x44 32 RO 0x00000000 
The Queue 1 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow.
MTL_RxQ1_Debug 0x48 32 RO 0x00000000 
The Queue 1 Receive Debug register gives the debug status of various blocks related to the Receive queue.
MTL_RxQ1_Control 0x4C 32 RW 0x00000000 
The Queue 1 Receive Control register controls the receive arbitration and passing of received packets to the application.
MTL_RxQ1_Flow_Control 0x50 32 RW 0x00000000 
This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control.
MTL_Q1_Interrupt_Enable 0x70 32 RW 0x00000000 
This register contains the interrupt enable bits for Traffic class/Queue 1.
MTL_Q1_Interrupt_Status 0x74 32 RW 0x00000000 
This register contains the interrupt status bits for Traffic class/Queue 1.