1EMAC1_DWCXG_DMA Address Map

DMA Common/General Registers.
Module Instance Base Address End Address
u_emac1__apb_reg_config_slave__10820000__DWCXG_DMA__SEG_L4_MP_emac1_s_0x0_0x10000 0x10823000 0x108230FF
Register Offset Width Access Reset Value Description
DMA_Mode 0x0 32 RW 0x00000000 
The Bus Mode register establishes the bus operating modes for the DMA.
DMA_SysBus_Mode 0x4 32 RW 0x01010000 
The System Bus mode register controls the behavior of the AXI master. It mainly controls burst splitting and number of outstanding requests.
DMA_Interrupt_Status 0x8 32 RO 0x00000000 
The application reads this Interrupt Status register during interrupt service routine or polling to determine the interrupt status of DMA channels, MTL queues, and the MAC.
AXI_Tx_AR_ACE_Control 0x10 32 RW 0x00000000 
This register is used to control the AXI4 Cache Coherency Signals for read transactions by all the Transmit DMA channels. The following signals of the AXI4 interface are driven with different values as programmed for corresponding type (descriptor, buffer1, buffer2) of access.
   - arcache_m_o[3:0]
   - ardomain_m_o[1:0]
AXI_Rx_AW_ACE_Control 0x18 32 RW 0x00000000 
This register is used to control the Cache Coherency Signals of the AXI4-ACE Lite on the Receive DMA. The programmable controllability is supported on the following signals of the AXI Write channel.
   - awcache_m_o[3:0]
   - awdomain_m_o[1:0]
AXI_TxRx_AWAR_ACE_Control 0x1C 32 RW 0x00000000 
This register is used to control the AXI4 Cache Coherency Signals for Descriptor write transactions by all the TxDMA channels and Descriptor read transactions by all the RxDMA channels. It also controls the values to be driven on awprot_m_o and arprot_m_o.
DMA_Debug_Status0 0x20 32 RO 0x00000000 
The Debug Status 0 register gives the Receive and Transmit process status for DMA Channel 0 - Channel 2 for debugging purpose.
DMA_Debug_Status1 0x24 32 RO 0x00000000 
The Debug Status1 register gives the per Transmit DMA active status.
DMA_Debug_Status3 0x2C 32 RO 0x00000000 
The Debug Status3 register gives the per Receive DMA active status.
DMA_Tx_EDMA_Control 0x40 32 RW 0x00000000 
The DMA_Tx_EDMA_Control register controls the sequence of all TxDMA operations with the DMA engine.
DMA_Rx_EDMA_Control 0x44 32 RW 0x00000000 
The DMA_Rx_EDMA_Control register controls the sequence of all RxDMA operations with the DMA engine.
AXI_LPI_Entry_Interval 0x50 32 RW 0x00000000 
This register is used to control the AXI LPI entry interval.
DMA_TBS_CTRL0 0x54 32 RW 0x00000000 
This register is used to control the TBS0 attributes.
DMA_TBS_CTRL1 0x58 32 RW 0x00000000 
This register is used to control the TBS1 attributes.
DMA_TBS_CTRL2 0x5C 32 RW 0x00000000 
This register is used to control the TBS2 attributes.
DMA_TBS_CTRL3 0x60 32 RW 0x00000000 
This register is used to control the TBS3 attributes.
DMA_CH_Ind_Ctrl 0x80 32 RW 0x00000000 
This register is used to program Indirect Access DMA configuration registers
DMA_CH_Ind_Data 0x84 32 RW 0x00000000 
This register holds the read/write data for Indirect Access of the registers indicated by DMA_<MSEL>_<AOFF>. During the read access, this field contains valid read data only after the OB bit is reset. During the write access, this field must be valid prior setting the OB bit in the DMA_CH_Ind_Data register. Once auto increment is set, application is allowed to write without setting OB bit of DMA_CH_Ind_Ctrl register.