0EMAC0_DWCXG_MTL_TCQ0 Summary

MTL Traffic Class/Queue (#i) Registers.

Base Address: 0x10811100


Register Address Offset	Bit Fields
`u_emac0__apb_reg_config_slave__10810000__DWCXG_MTL_TCQ0__SEG_L4_MP_emac0_s_0x0_0x10000`
`MTL_TxQ0_Operation_Mode` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_y` `RO 0x0`									`TQS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_y` `RO 0x0`					`Q2TCMAP` `RW 0x0`			`Reserved_7` `RO 0x0`	`TTC` `RW 0x0`			`TXQEN` `RW 0x0`		`TSF` `RW 0x0`	`FTQ` `RW 0x0`
`MTL_TxQ0_Underflow` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UFCNTOVF` `RO 0x0`	`Reserved_14_11` `RO 0x0`				`UFPKTCNT` `RO 0x0`
`MTL_TxQ0_Debug` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_6` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_6` `RO 0x0`										`TRCPSTS` `RO 0x0`	`TXQSTS` `RO 0x0`	`TWCSTS` `RO 0x0`	`TRCSTS` `RO 0x0`		`TCPAUSED` `RO 0x0`
`MTL_TC0_ETS_Control` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_7` `RO 0x0`									`Reserved_SLC` `RO 0x0`			`Reserved_CC` `RO 0x0`	`CBSEN` `RO 0x0`	`TSA` `RW 0x0`
`MTL_TC0_ETS_Status` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_24` `RO 0x0`								`ABS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ABS` `RO 0x0`
`MTL_TC0_Quantum_Weight` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_21` `RO 0x0`											`QW` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`QW` `RW 0x0`
`MTL_RxQ0_Operation_Mode` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_y` `RO 0x0`										`RQS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_8` `RO 0x0`								`EHFC` `RW 0x0`	`DIS_TCP_EF` `RW 0x0`	`RSF` `RW 0x0`	`FEF` `RW 0x0`	`FUF` `RW 0x0`	`Reserved_2` `RO 0x0`	`RTC` `RW 0x0`
`MTL_RxQ0_Missed_Pkt_Overflow_Cnt` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MISCNTOVF` `RO 0x0`	`Reserved_30_27` `RO 0x0`				`MISPKTCNT` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`OVFCNTOVF` `RO 0x0`	`Reserved_14_11` `RO 0x0`				`OVFPKTCNT` `RO 0x0`
`MTL_RxQ0_Debug` `0x72` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_30` `RO 0x0`		`PRXQ` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_6` `RO 0x0`										`RXQSTS` `RO 0x0`		`Reserved_3` `RO 0x0`	`RRCSTS` `RO 0x0`		`RWCSTS` `RO 0x0`
`MTL_RxQ0_Control` `0x76` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_4` `RO 0x0`												`RXQ_PKT_ARBIT` `RW 0x0`	`RXQ_WEGT` `RW 0x0`
`MTL_RxQ0_Flow_Control` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_y` `RO 0x0`										`RFD` `RW 0x0`					`Reserved_16_y` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_16_y` `RO 0x0`										`RFA` `RW 0x0`					`Reserved_0` `RO 0x0`
`MTL_Q0_Interrupt_Enable` `0x112` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_17` `RO 0x0`															`RXOIE` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_2` `RO 0x0`														`ABPSIE` `RW 0x0`	`TXUIE` `RW 0x0`
`MTL_Q0_Interrupt_Status` `0x116` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_17` `RO 0x0`															`RXOVFIS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_2` `RO 0x0`														`ABPSIS` `RW 0x0`	`TXUNFIS` `RW 0x0`