0EMAC0_DWCXG_MTL Summary

Mac Transaction Layer (MTL) Common/General Registers.

Base Address: 0x10811000


Register Address Offset	Bit Fields
`u_emac0__apb_reg_config_slave__10810000__DWCXG_MTL__SEG_L4_MP_emac0_s_0x0_0x10000`
`MTL_Operation_Mode` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_7` `RO 0x0`									`ETSALG` `RW 0x0`		`Reserved_4_3` `RO 0x0`		`RAA` `RW 0x0`	`Reserved_FTS` `RO 0x0`	`Reserved_0` `RO 0x0`
`MTL_Debug_Control` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_19` `RO 0x0`													`Reserved_EIEC` `RO 0x0`	`Reserved_EIAEE` `RO 0x0`	`Reserved_EIEE` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15` `RO 0x0`	`PKTIE` `RW 0x0`	`FIFOSEL` `RW 0x0`		`FIFOWREN` `RW 0x0`	`FIFORDEN` `RW 0x0`	`RSTSEL` `RW 0x0`	`RSTALL` `RW 0x0`	`Reserved_7` `RO 0x0`	`PKTSTATE` `RW 0x0`		`Reserved_4` `RO 0x0`	`BYTEEN` `RW 0x0`		`DBGMOD` `RW 0x0`	`FDBGEN` `RW 0x0`
`MTL_Debug_Status` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`LOCR` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_9` `RO 0x0`							`PKTI` `RW 0x0`	`Reserved_7_5` `RO 0x0`			`BYTEEN` `RO 0x3`		`PKTSTATE` `RO 0x0`		`FIFOBUSY` `RO 0x0`
`MTL_FIFO_Debug_Data` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`FDBGDATA` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`FDBGDATA` `RW 0x0`
`MTL_Interrupt_Status` `0x32` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_24` `RO 0x0`								`Reserved_MTLPIS` `RO 0x0`	`Reserved_22_21` `RO 0x0`		`Reserved_SGFIS` `RO 0x0`	`TINS` `RO 0x0`	`ESTIS` `RO 0x0`	`DBGIS` `RO 0x0`	`MACIS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Q15IS` `RO 0x0`	`Q14IS` `RO 0x0`	`Q13IS` `RO 0x0`	`Q12IS` `RO 0x0`	`Q11IS` `RO 0x0`	`Q10IS` `RO 0x0`	`Q9IS` `RO 0x0`	`Q8IS` `RO 0x0`	`Q7IS` `RO 0x0`	`Q6IS` `RO 0x0`	`Q5IS` `RO 0x0`	`Q4IS` `RO 0x0`	`Q3IS` `RO 0x0`	`Q2IS` `RO 0x0`	`Q1IS` `RO 0x0`	`Q0IS` `RO 0x0`
`MTL_RxQ_DMA_Map0` `0x48` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Q3DDMACH` `RW 0x0`	`Reserved_30_y` `RO 0x0`				`Q3MDMACH` `RW 0x0`			`Q2DDMACH` `RW 0x0`	`Reserved_22_y` `RO 0x0`				`Q2MDMACH` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Q1DDMACH` `RW 0x0`	`Reserved_14_y` `RO 0x0`				`Q1MDMACH` `RW 0x0`			`Q0DDMACH` `RW 0x0`	`Reserved_6_y` `RO 0x0`				`Q0MDMACH` `RW 0x0`
`MTL_RxQ_DMA_Map1` `0x52` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Q7DDMACH` `RW 0x0`	`Reserved_30_y` `RO 0x0`				`Q7MDMACH` `RW 0x0`			`Q6DDMACH` `RW 0x0`	`Reserved_22_y` `RO 0x0`				`Q6MDMACH` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Q5DDMACH` `RW 0x0`	`Reserved_14_y` `RO 0x0`				`Q5MDMACH` `RW 0x0`			`Q4DDMACH` `RW 0x0`	`Reserved_6_y` `RO 0x0`				`Q4MDMACH` `RW 0x0`
`MTL_TC_Prty_Map0` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PSTC3` `RW 0x0`								`PSTC2` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PSTC1` `RW 0x0`								`PSTC0` `RW 0x0`
`MTL_TC_Prty_Map1` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PSTC7` `RW 0x0`								`PSTC6` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PSTC5` `RW 0x0`								`PSTC4` `RW 0x0`
`MTL_TBS_CTRL` `0x72` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`LEOS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`LEOS` `RW 0x0`								`Reserved_7` `RO 0x0`	`LEGOS` `RW 0x0`			`Reserved_3` `RO 0x0`	`TIEN` `RW 0x0`	`LEOV` `RW 0x0`	`ESTM` `RW 0x0`
`MTL_TBS_STATS` `0x76` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_x` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_x` `RO 0x0`								`EDQN` `RW 0x0`
`MTL_EST_Control` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PTOV` `RW 0x0`									`CTOV` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CTOV` `RW 0x0`					`TILS` `RW 0x0`			`LCSE` `RW 0x0`		`DFBS` `RW 0x0`	`DDBF` `RW 0x0`	`QHLBF` `RW 0x0`	`Reserved_2` `RO 0x0`	`SSWL` `RW 0x0`	`EEST` `RW 0x0`
`MTL_EST_Overhead` `0x84` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_21` `RO 0x0`											`Reserved_ABYT` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_8` `RO 0x0`								`OVHD` `RW 0x0`
`MTL_EST_Status` `0x88` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_20` `RO 0x0`												`CGSN` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BTRL` `RO 0x0`								`SWOL` `RO 0x0`	`Reserved_6_5` `RO 0x0`		`CGCE` `RW 0x0`	`HLBS` `RO 0x0`	`HLBF` `RO 0x0`	`BTRE` `RW 0x0`	`SWLC` `RW 0x0`
`MTL_EST_Sch_Error` `0x96` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_x` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_x` `RO 0x0`								`SETN` `RW 0x0`
`MTL_EST_Frm_Size_Error` `0x100` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_x` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_x` `RO 0x0`								`FETN` `RW 0x0`
`MTL_EST_Frm_Size_Capture` `0x104` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_x` `RO 0x0`													`HBFQ` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15` `RO 0x0`	`HBFS` `RO 0x0`
`MTL_EST_Intr_Enable` `0x112` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`CGCE` `RW 0x0`	`IEHS` `RW 0x0`	`IEHF` `RW 0x0`	`IEBE` `RW 0x0`	`IECC` `RW 0x0`
`MTL_GCL_Control` `0x128` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_24` `RO 0x0`								`GCLEIEC` `RO 0x0`	`GCLEIAEE` `RO 0x0`	`GCLEIEE` `RO 0x0`	`Reserved_20_y` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`								`Reserved_7_6` `RO 0x0`		`DBGB` `RW 0x0`	`DBGM` `RW 0x0`	`Reserved_GCLS` `RO 0x0`	`GCRR` `RW 0x0`	`R1W0` `RW 0x0`	`SRWO` `RW 0x0`
`MTL_GCL_Data` `0x132` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`GCD` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`GCD` `RW 0x0`
`MTL_FPE_CTRL_STS` `0x144` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_29` `RO 0x0`			`HRS` `RO 0x0`	`Reserved_27_17` `RO 0x0`											`PHRSC` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PEC` `RW 0x0`								`LBHT` `RW 0x0`	`Reserved_6_2` `RO 0x0`					`AFSZ` `RW 0x0`
`MTL_FPE_Advance` `0x148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RADV` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`HADV` `RW 0x0`