0EMAC0_DWCXG_DMA_CH3 Summary

DMA Channel (#i) Registers.

Base Address: 0x10813280


Register Address Offset	Bit Fields
`u_emac0__apb_reg_config_slave__10810000__DWCXG_DMA_CH3__SEG_L4_MP_emac0_s_0x0_0x10000`
`DMA_CH3_Control` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_25` `RO 0x0`							`SPH` `RW 0x0`	`Reserved_23_21` `RO 0x0`			`DSL` `RW 0x0`			`Reserved_17` `RO 0x0`	`PBLx8` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_14` `RO 0x0`		`MSS` `RW 0x0`
`DMA_CH3_Tx_Control` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31` `RO 0x0`	`TFSEL` `RW 0x0`		`Reserved_EDSE` `RO 0x0`	`TQOS` `RW 0x0`				`Reserved_23_22` `RO 0x0`		`TxPBL` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_IPBL` `RO 0x0`	`Reserved_14_13` `RO 0x0`		`TSE` `RW 0x0`	`Reserved_11_5` `RO 0x0`							`Reserved_OSP` `RO 0x0`	`Reserved_3_1` `RO 0x0`			`ST` `RW 0x0`
`DMA_CH3_Rx_Control` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RPF` `RW 0x0`	`Reserved_30_28` `RO 0x0`			`RQOS` `RW 0x0`				`Reserved_23_22` `RO 0x0`		`RxPBL` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15` `RO 0x0`	`RBSZ` `RW 0x0`											`Reserved_x_1` `RO 0x0`			`SR` `RW 0x0`
`DMA_CH3_Slot_Function_Control_Status` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_20` `RO 0x0`												`RSN` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_2` `RO 0x0`														`ASC` `RW 0x0`	`ESC` `RW 0x0`
`DMA_CH3_TxDesc_List_HAddress` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_y` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_y` `RO 0x0`								`TDESHA` `RW 0x0`
`DMA_CH3_TxDesc_List_LAddress` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TDESLA` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TDESLA` `RW 0x0`													`Reserved_x_0` `RO 0x0`
`DMA_CH3_RxDesc_List_HAddress` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_y` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_y` `RO 0x0`								`RDESHA` `RW 0x0`
`DMA_CH3_RxDesc_List_LAddress` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RDESLA` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RDESLA` `RW 0x0`													`Reserved_x_0` `RO 0x0`
`DMA_CH3_TxDesc_Tail_LPointer` `0x36` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TDT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TDT` `RW 0x0`													`Reserved_x_0` `RO 0x0`
`DMA_CH3_RxDesc_Tail_LPointer` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RDT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RDT` `RW 0x0`													`Reserved_x_0` `RO 0x0`
`DMA_CH3_Tx_Control2` `0x48` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_y` `RO 0x0`						`ORRQ` `RW 0x0`		`Reserved_23_12` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TDRL` `RW 0x0`
`DMA_CH3_Rx_Control2` `0x52` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_y` `RO 0x0`						`OWRQ` `RW 0x0`		`ARBS` `RW 0x0`							`Reserved_x_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RDRL` `RW 0x0`
`DMA_CH3_Interrupt_Enable` `0x56` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NIE` `RW 0x0`	`AIE` `RW 0x0`	`CDEE` `RW 0x0`	`FBEE` `RW 0x0`	`Reserved_11_10` `RO 0x0`		`DDEE` `RW 0x0`	`RSE` `RW 0x0`	`RBUE` `RW 0x0`	`RIE` `RW 0x0`	`Reserved_5_3` `RO 0x0`			`TBUE` `RW 0x0`	`TXSE` `RW 0x0`	`TIE` `RW 0x0`
`DMA_CH3_Rx_Interrupt_Watchdog_Timer` `0x60` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PSEL` `RW 0x0`	`Reserved_30_26` `RO 0x0`					`RBCT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_14` `RO 0x0`		`RWTU` `RW 0x0`		`Reserved_11_8` `RO 0x0`				`RWT` `RW 0x0`
`DMA_CH3_Current_App_TxDesc_L` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CURTDESAPTR` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CURTDESAPTR` `RO 0x0`
`DMA_CH3_Current_App_RxDesc_L` `0x76` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CURRDESAPTR` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CURRDESAPTR` `RO 0x0`
`DMA_CH3_Current_App_TxBuffer_H` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_y` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_y` `RO 0x0`								`CURTBUFAPTRH` `RO 0x0`
`DMA_CH3_Current_App_TxBuffer_L` `0x84` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CURTBUFAPTR` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CURTBUFAPTR` `RO 0x0`
`DMA_CH3_Current_App_RxBuffer_H` `0x88` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_y` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_y` `RO 0x0`								`CURRBUFAPTRH` `RO 0x0`
`DMA_CH3_Current_App_RxBuffer_L` `0x92` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CURRBUFAPTR` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CURRBUFAPTR` `RO 0x0`
`DMA_CH3_Status` `0x96` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_22` `RO 0x0`										`REB` `RW 0x0`			`TEB` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NIS` `RW 0x0`	`AIS` `RW 0x0`	`CDE` `RW 0x0`	`FBE` `RW 0x0`	`Reserved_11_10` `RO 0x0`		`DDE` `RW 0x0`	`RPS` `RW 0x0`	`RBU` `RW 0x0`	`RI` `RW 0x0`	`Reserved_5_3` `RO 0x0`			`TBU` `RW 0x0`	`TPS` `RW 0x0`	`TI` `RW 0x0`
`DMA_CH3_Debug_Status` `0x100` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31` `RO 0x0`	`RDWS` `RO 0x0`			`RDTS` `RO 0x0`									`RDFS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15` `RO 0x0`	`TDWS` `RO 0x0`			`TDTS` `RO 0x0`				`TDRS` `RO 0x0`		`TDXS` `RO 0x0`			`TDFS` `RO 0x0`
`DMA_CH3_Desc_Mem_Cache_Fill_Level` `0x104` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_y` `RO 0x0`									`RX_FILL_LVL` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_y` `RO 0x0`									`TX_FILL_LVL` `RO 0x0`
`DMA_CH3_Miss_Packet_Cnt` `0x108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MFCO` `RO 0x0`	`Reserved_14_11` `RO 0x0`				`MFC` `RO 0x0`
`DMA_CH3_Tx_Data_Xfer_Ring_Offset` `0x112` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_12` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DESC_OFFSET` `RO 0x0`
`DMA_CH3_Rx_Data_Xfer_Ring_Offset` `0x116` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_12` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DESC_OFFSET` `RO 0x0`
`DMA_CH3_Tx_Desc_Write_Ring_Offset` `0x120` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_12` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DESC_OFFSET` `RO 0x0`
`DMA_CH3_Rx_Desc_Write_Ring_Offset` `0x124` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_12` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DESC_OFFSET` `RO 0x0`