0EMAC0_DWCXG_DMA Summary

DMA Common/General Registers.

Base Address: 0x10813000


Register Address Offset	Bit Fields
`u_emac0__apb_reg_config_slave__10810000__DWCXG_DMA__SEG_L4_MP_emac0_s_0x0_0x10000`
`DMA_Mode` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_14` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_14` `RO 0x0`		`INTM` `RW 0x0`		`Reserved_11_9` `RO 0x0`			`DSPW` `RW 0x0`	`Reserved_7_6` `RO 0x0`		`Reserved_TMRP` `RO 0x0`	`TDRP` `RW 0x0`	`Reserved_3_1` `RO 0x0`			`SWR` `RW 0x0`
`DMA_SysBus_Mode` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_30` `RO 0x0`			`WR_OSR_LMT` `RW 0x1`					`Reserved_23_22` `RO 0x0`			`RD_OSR_LMT` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`EN_LPI` `RW 0x0`	`LPI_XIT_PKT` `RW 0x0`	`ONEKBBE` `RW 0x0`	`AAL` `RW 0x0`	`EAME` `RW 0x0`	`AALE` `RW 0x0`	`Reserved_9_8` `RO 0x0`		`BLEN256` `RW 0x0`	`BLEN128` `RW 0x0`	`BLEN64` `RW 0x0`	`BLEN32` `RW 0x0`	`BLEN16` `RW 0x0`	`BLEN8` `RW 0x0`	`BLEN4` `RW 0x0`	`UBL` `RW 0x0`
`DMA_Interrupt_Status` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_18` `RO 0x0`														`MACIS` `RO 0x0`	`MTLIS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DC15TC8IS` `RO 0x0`								`DC7IS` `RO 0x0`	`DC6IS` `RO 0x0`	`DC5IS` `RO 0x0`	`DC4IS` `RO 0x0`	`DC3IS` `RO 0x0`	`DC2IS` `RO 0x0`	`DC1IS` `RO 0x0`	`DC0IS` `RO 0x0`
`AXI_Tx_AR_ACE_Control` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_22` `RO 0x0`										`THD` `RW 0x0`		`THC` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_14` `RO 0x0`		`TED` `RW 0x0`		`TEC` `RW 0x0`				`Reserved_7_6` `RO 0x0`		`TDRD` `RW 0x0`		`TDRC` `RW 0x0`
`AXI_Rx_AW_ACE_Control` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_30` `RO 0x0`		`RDD` `RW 0x0`		`RDC` `RW 0x0`				`Reserved_23_22` `RO 0x0`		`RHD` `RW 0x0`		`RHC` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_14` `RO 0x0`		`RPD` `RW 0x0`		`RPC` `RW 0x0`				`Reserved_7_6` `RO 0x0`		`RDWD` `RW 0x0`		`RDWC` `RW 0x0`
`AXI_TxRx_AWAR_ACE_Control` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_23` `RO 0x0`									`WRP` `RW 0x0`			`Reserved_19` `RO 0x0`	`RDP` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_14` `RO 0x0`		`RDRD` `RW 0x0`		`RDRC` `RW 0x0`				`Reserved_7_6` `RO 0x0`		`TDWD` `RW 0x0`		`TDWC` `RW 0x0`
`DMA_Debug_Status0` `0x32` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TPS2` `RO 0x0`				`RPS2` `RO 0x0`				`TPS1` `RO 0x0`				`RPS1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TPS0` `RO 0x0`				`RPS0` `RO 0x0`				`Reserved_7_2` `RO 0x0`						`AXRHSTS` `RO 0x0`	`AXWHSTS` `RO 0x0`
`DMA_Debug_Status1` `0x36` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_x` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_x` `RO 0x0`								`TDAS` `RO 0x0`
`DMA_Debug_Status3` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_x` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_x` `RO 0x0`								`RDAS` `RO 0x0`
`DMA_Tx_EDMA_Control` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TEDM` `RW 0x0`		`Reserved_29_y` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_29_y` `RO 0x0`														`TDPS` `RW 0x0`
`DMA_Rx_EDMA_Control` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`REDM` `RW 0x0`		`Reserved_29_y` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_29_y` `RO 0x0`														`RDPS` `RW 0x0`
`AXI_LPI_Entry_Interval` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_4` `RO 0x0`												`LPIEI` `RW 0x0`
`DMA_TBS_CTRL0` `0x84` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`FTOS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`FTOS` `RW 0x0`								`Reserved_7` `RO 0x0`	`FGOS` `RW 0x0`			`Reserved_3_1` `RO 0x0`			`FTOV` `RW 0x0`
`DMA_TBS_CTRL1` `0x88` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`FTOS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`FTOS` `RW 0x0`								`Reserved_7` `RO 0x0`	`FGOS` `RW 0x0`			`Reserved_3_1` `RO 0x0`			`FTOV` `RW 0x0`
`DMA_TBS_CTRL2` `0x92` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`FTOS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`FTOS` `RW 0x0`								`Reserved_7` `RO 0x0`	`FGOS` `RW 0x0`			`Reserved_3_1` `RO 0x0`			`FTOV` `RW 0x0`
`DMA_TBS_CTRL3` `0x96` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`FTOS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`FTOS` `RW 0x0`								`Reserved_7` `RO 0x0`	`FGOS` `RW 0x0`			`Reserved_3_1` `RO 0x0`			`FTOV` `RW 0x0`
`DMA_CH_Ind_Ctrl` `0x128` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_20` `RO 0x0`												`MSEL` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_12` `RO 0x0`				`AOFF` `RW 0x0`				`Reserved_7_6` `RO 0x0`		`AUTO` `RW 0x0`		`Reserved_3_2` `RO 0x0`		`CT` `RW 0x0`	`OB` `RW 0x0`
`DMA_CH_Ind_Data` `0x132` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_7` `RO 0x0`									`WT` `RW 0x0`