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Agilex™ 5 HPS Register Map for ES Devices (Preliminary)
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Hard Processor System (HPS) Address Map for the Agilex™ 5 SoC
OCRAM_memory Address Block Group
OCRAM_512K Address Map
SDMMC Address Block Group
HRS Address Map
HRS Summary
HRS00
HRS01
HRS02
HRS03
HRS04
HRS05
HRS06
HRS07
HRS08
HRS09
HRS10
HRS12
HRS13
HRS14
HRS16
HRS29
HRS30
HRS31
HRS32
HRS33
HRS34
SRS Address Map
SRS Summary
SRS00
SRS01
SRS02
SRS03
SRS04
SRS05
SRS06
SRS07
SRS08
SRS09
SRS10
SRS11
SRS12
SRS13
SRS14
SRS15
SRS16
SRS17
SRS18
SRS19
SRS20
SRS21
SRS22
SRS23
SRS24
SRS25
SRS26
SRS27
SRS30
SRS31
CRS Address Map
CRS Summary
CRS63
CQRS Address Map
CQRS Summary
CQRS00
CQRS01
CQRS02
CQRS03
CQRS04
CQRS05
CQRS06
CQRS07
CQRS08
CQRS09
CQRS10
CQRS11
CQRS12
CQRS13
CQRS14
CQRS16
CQRS17
CQRS18
CQRS20
CQRS21
CQRS22
CQRS23
EMAC0 Address Block Group
0EMAC0_DWCXG_CORE Address Map
0EMAC0_DWCXG_CORE Summary
MAC_Tx_Configuration
MAC_Rx_Configuration
MAC_Packet_Filter
MAC_WD_JB_Timeout
MAC_Hash_Table_Reg0
MAC_Hash_Table_Reg1
MAC_VLAN_Tag_Ctrl
MAC_VLAN_Tag_Data
MAC_VLAN_Hash_Table
MAC_VLAN_Incl
MAC_Inner_VLAN_Incl
MAC_Rx_Eth_Type_Match
MAC_Q0_Tx_Flow_Ctrl
MAC_Q1_Tx_Flow_Ctrl
MAC_Q2_Tx_Flow_Ctrl
MAC_Q3_Tx_Flow_Ctrl
MAC_Q4_Tx_Flow_Ctrl
MAC_Q5_Tx_Flow_Ctrl
MAC_Q6_Tx_Flow_Ctrl
MAC_Q7_Tx_Flow_Ctrl
MAC_Rx_Flow_Ctrl
MAC_RxQ_Ctrl4
MAC_RxQ_Ctrl5
MAC_RxQ_Ctrl0
MAC_RxQ_Ctrl1
MAC_RxQ_Ctrl2
MAC_RxQ_Ctrl3
MAC_Interrupt_Status
MAC_Interrupt_Enable
MAC_Rx_Tx_Status
MAC_Version
MAC_Debug
MAC_HW_Feature0
MAC_HW_Feature1
MAC_HW_Feature2
MAC_HW_Feature3
MAC_HW_Feature4
MAC_Extended_Configuration
MAC_Ext_Cfg1
MDIO_Single_Command_Address
MDIO_Single_Command_Control_Data
MDIO_Continuous_Write_Address
MDIO_Continuous_Write_Data
MDIO_Continuous_Scan_Port_Enable
MDIO_Interrupt_Status
MDIO_Interrupt_Enable
MDIO_Port_Connect_Disconnect_Status
MDIO_Clause_22_Port
MDIO_Port_Nx4_Indirect_Control
MDIO_PortNx4P0_Device_In_Use
MDIO_PortNx4P0_Link_Status
MDIO_PortNx4P0_Alive_Status
MDIO_PortNx4P1_Device_In_Use
MDIO_PortNx4P1_Link_Status
MDIO_PortNx4P1_Alive_Status
MDIO_PortNx4P2_Device_In_Use
MDIO_PortNx4P2_Link_Status
MDIO_PortNx4P2_Alive_Status
MDIO_PortNx4P3_Device_In_Use
MDIO_PortNx4P3_Link_Status
MDIO_PortNx4P3_Alive_Status
MAC_GPIO_Control
MAC_GPIO_Status
MAC_FPE_CTRL_STS
MAC_CSR_SW_Ctrl
MAC_Address0_High
MAC_Address0_Low
MAC_Address1_High
MAC_Address1_Low
MAC_Address2_High
MAC_Address2_Low
MAC_Address3_High
MAC_Address3_Low
MAC_Address4_High
MAC_Address4_Low
MAC_Address5_High
MAC_Address5_Low
MAC_Address6_High
MAC_Address6_Low
MAC_Address7_High
MAC_Address7_Low
MAC_Address8_High
MAC_Address8_Low
MAC_Address9_High
MAC_Address9_Low
MAC_Address10_High
MAC_Address10_Low
MAC_Address11_High
MAC_Address11_Low
MAC_Address12_High
MAC_Address12_Low
MAC_Address13_High
MAC_Address13_Low
MAC_Address14_High
MAC_Address14_Low
MAC_Address15_High
MAC_Address15_Low
MAC_Address16_High
MAC_Address16_Low
MAC_Address17_High
MAC_Address17_Low
MAC_Address18_High
MAC_Address18_Low
MAC_Address19_High
MAC_Address19_Low
MAC_Address20_High
MAC_Address20_Low
MAC_Address21_High
MAC_Address21_Low
MAC_Address22_High
MAC_Address22_Low
MAC_Address23_High
MAC_Address23_Low
MAC_Address24_High
MAC_Address24_Low
MAC_Address25_High
MAC_Address25_Low
MAC_Address26_High
MAC_Address26_Low
MAC_Address27_High
MAC_Address27_Low
MAC_Address28_High
MAC_Address28_Low
MAC_Address29_High
MAC_Address29_Low
MAC_Address30_High
MAC_Address30_Low
MAC_Address31_High
MAC_Address31_Low
MAC_Indir_Access_Ctrl
MAC_Indir_Access_Data
MMC_Control
MMC_Rx_Interrupt
MMC_Tx_Interrupt
MMC_Receive_Interrupt_Enable
MMC_Transmit_Interrupt_Enable
Tx_Octet_Count_Good_Bad_Low
Tx_Octet_Count_Good_Bad_High
Tx_Packet_Count_Good_Bad_Low
Tx_Broadcast_Packets_Good_Low
Tx_Multicast_Packets_Good_Low
Tx_64Octets_Packets_Good_Bad_Low
Tx_65To127Octets_Packets_Good_Bad_Low
Tx_128To255Octets_Packets_Good_Bad_Low
Tx_256To511Octets_Packets_Good_Bad_Low
Tx_512To1023Octets_Packets_Good_Bad_Low
Tx_1024ToMaxOctets_Packets_Good_Bad_Low
Tx_Unicast_Packets_Good_Bad_Low
Tx_Multicast_Packets_Good_Bad_Low
Tx_Broadcast_Packets_Good_Bad_Low
Tx_Underflow_Error_Packets_Low
Tx_Octet_Count_Good_Low
Tx_Octet_Count_Good_High
Tx_Packet_Count_Good_Low
Tx_Pause_Packets_Low
Tx_VLAN_Packets_Good_Low
Rx_Packet_Count_Good_Bad_Low
Rx_Octet_Count_Good_Bad_Low
Rx_Octet_Count_Good_Bad_High
Rx_Octet_Count_Good_Low
Rx_Octet_Count_Good_High
Rx_Broadcast_Packets_Good_Low
Rx_Multicast_Packets_Good_Low
Rx_CRC_Error_Packets_Low
Rx_Runt_Error_Packets
Rx_Jabber_Error_Packets
Rx_Undersize_Packets_Good
Rx_Oversize_Packets_Good
Rx_64Octets_Packets_Good_Bad_Low
Rx_65To127Octets_Packets_Good_Bad_Low
Rx_128To255Octets_Packets_Good_Bad_Low
Rx_256To511Octets_Packets_Good_Bad_Low
Rx_512To1023Octets_Packets_Good_Bad_Low
Rx_1024ToMaxOctets_Packets_Good_Bad_Low
Rx_Unicast_Packets_Good_Low
Rx_Length_Error_Packets_Low
Rx_OutofRange_Packets_Low
Rx_Pause_Packets_Low
Rx_FIFOOverflow_Packets_Low
Rx_VLAN_Packets_Good_Bad_Low
Rx_Watchdog_Error_Packets
Rx_Discard_Packets_Good_Bad_Low
Rx_Discard_Octets_Good_Bad_Low
Rx_Discard_Octets_Good_Bad_High
Rx_Alignment_Error_Packets
MMC_FPE_Tx_Interrupt
MMC_FPE_Tx_Interrupt_Mask
MMC_Tx_FPE_Fragment_Cntr
MMC_Tx_Hold_Req_Cntr
MMC_Tx_Gate_Orun_Cntr_Low
MMC_Tx_Gate_Orun_Cntr_High
MMC_FPE_Rx_Interrupt
MMC_FPE_Rx_Interrupt_Mask
MMC_Rx_Packet_Assembly_Err_Cntr
MMC_Rx_Packet_SMD_Err_Cntr
MMC_Rx_Packet_Assembly_OK_Cntr
MMC_Rx_FPE_Fragment_Cntr
Tx_Single_Collision_Good_Packets
Tx_Multiple_Collision_Good_Packets
Tx_Deferred_Packets
Tx_Late_Collision_Packets
Tx_Excessive_Collision_Packets
Tx_Carrier_Error_Packets
Tx_Excessive_Deferral_Error
MMC_IPC_Rx_Interrupt_Mask
MMC_IPC_Rx_Interrupt
RxIPv4_Good_Packets_Low
RxIPv4_Header_Error_Packets_Low
RxIPv4_No_Payload_Packets_Low
RxIPv4_Fragmented_Packets_Low
RxIPv4_UDP_Checksum_Disabled_Packets_Low
RxIPv6_Good_Packets_Low
RxIPv6_Header_Error_Packets_Low
RxIPv6_No_Payload_Packets_Low
RxUDP_Good_Packets_Low
RxUDP_Error_Packets_Low
RxTCP_Good_Packets_Low
RxTCP_Error_Packets_Low
RxICMP_Good_Packets_Low
RxICMP_Error_Packets_Low
RxIPv4_Good_Octets_Low
RxIPv4_Header_Error_Octets_Low
RxIPv4_No_Payload_Octets_Low
RxIPv4_Fragmented_Octets_Low
RxIPv4_UDP_Checksum_Disable_Octets_Low
RxIPv6_Good_Octets_Low
RxIPv6_Header_Error_Octets_Low
RxIPv6_No_Payload_Octets_Low
RxUDP_Good_Octets_Low
RxUDP_Error_Octets_Low
RxTCP_Good_Octets_Low
RxTCP_Error_Octets_Low
RxICMP_Good_Octets_Low
RxICMP_Error_Octets_Low
MAC_L3_L4_Address_Control
MAC_L3_L4_Data
MAC_ARP_Address
MAC_Timestamp_Control
MAC_Sub_Second_Increment
MAC_System_Time_Seconds
MAC_System_Time_Nanoseconds
MAC_System_Time_Seconds_Update
MAC_System_Time_Nanoseconds_Update
MAC_Timestamp_Addend
MAC_System_Time_Higher_Word_Seconds
MAC_Timestamp_Status
MAC_Tx_Timestamp_Status_Nanoseconds
MAC_Tx_Timestamp_Status_Seconds
MAC_Tx_Timestamp_Status_PktID
MAC_Auxiliary_Control
MAC_Auxiliary_Timestamp_Nanoseconds
MAC_Auxiliary_Timestamp_Seconds
MAC_Timestamp_Ingress_Asym_Corr
MAC_Timestamp_Egress_Asym_Corr
MAC_Timestamp_Ingress_Corr_Nanosecond
MAC_Timestamp_Ingress_Corr_Subnanosecond
MAC_Timestamp_Egress_Corr_Nanosecond
MAC_Timestamp_Egress_Corr_Subnanosecond
MAC_PPS_Control
MAC_PPS0_Target_Time_Seconds
MAC_PPS0_Target_Time_Nanoseconds
MAC_PPS0_Interval
MAC_PPS0_Width
MAC_PPS1_Target_Time_Seconds
MAC_PPS1_Target_Time_Nanoseconds
MAC_PPS1_Interval
MAC_PPS1_Width
MAC_PTO_Control
MAC_Source_Port_Identity0
MAC_Source_Port_Identity1
MAC_Source_Port_Identity2
MAC_Log_Message_Interval
0EMAC0_DWCXG_MTL Address Map
0EMAC0_DWCXG_MTL Summary
MTL_Operation_Mode
MTL_Debug_Control
MTL_Debug_Status
MTL_FIFO_Debug_Data
MTL_Interrupt_Status
MTL_RxQ_DMA_Map0
MTL_RxQ_DMA_Map1
MTL_TC_Prty_Map0
MTL_TC_Prty_Map1
MTL_TBS_CTRL
MTL_TBS_STATS
MTL_EST_Control
MTL_EST_Overhead
MTL_EST_Status
MTL_EST_Sch_Error
MTL_EST_Frm_Size_Error
MTL_EST_Frm_Size_Capture
MTL_EST_Intr_Enable
MTL_GCL_Control
MTL_GCL_Data
MTL_FPE_CTRL_STS
MTL_FPE_Advance
0EMAC0_DWCXG_MTL_TCQ0 Address Map
0EMAC0_DWCXG_MTL_TCQ0 Summary
MTL_TxQ0_Operation_Mode
MTL_TxQ0_Underflow
MTL_TxQ0_Debug
MTL_TC0_ETS_Control
MTL_TC0_ETS_Status
MTL_TC0_Quantum_Weight
MTL_RxQ0_Operation_Mode
MTL_RxQ0_Missed_Pkt_Overflow_Cnt
MTL_RxQ0_Debug
MTL_RxQ0_Control
MTL_RxQ0_Flow_Control
MTL_Q0_Interrupt_Enable
MTL_Q0_Interrupt_Status
0EMAC0_DWCXG_MTL_TCQ1 Address Map
0EMAC0_DWCXG_MTL_TCQ1 Summary
MTL_TxQ1_Operation_Mode
MTL_TxQ1_Underflow
MTL_TxQ1_Debug
MTL_TC1_ETS_Control
MTL_TC1_ETS_Status
MTL_TC1_Quantum_Weight
MTL_RxQ1_Operation_Mode
MTL_RxQ1_Missed_Pkt_Overflow_Cnt
MTL_RxQ1_Debug
MTL_RxQ1_Control
MTL_RxQ1_Flow_Control
MTL_Q1_Interrupt_Enable
MTL_Q1_Interrupt_Status
0EMAC0_DWCXG_MTL_TCQ2 Address Map
0EMAC0_DWCXG_MTL_TCQ2 Summary
MTL_TxQ2_Operation_Mode
MTL_TxQ2_Underflow
MTL_TxQ2_Debug
MTL_TC2_ETS_Control
MTL_TC2_ETS_Status
MTL_TC2_Quantum_Weight
MTL_RxQ2_Operation_Mode
MTL_RxQ2_Missed_Pkt_Overflow_Cnt
MTL_RxQ2_Debug
MTL_RxQ2_Control
MTL_RxQ2_Flow_Control
MTL_Q2_Interrupt_Enable
MTL_Q2_Interrupt_Status
0EMAC0_DWCXG_MTL_TCQ3 Address Map
0EMAC0_DWCXG_MTL_TCQ3 Summary
MTL_TxQ3_Operation_Mode
MTL_TxQ3_Underflow
MTL_TxQ3_Debug
MTL_TC3_ETS_Control
MTL_TC3_ETS_Status
MTL_TC3_Quantum_Weight
MTL_RxQ3_Operation_Mode
MTL_RxQ3_Missed_Pkt_Overflow_Cnt
MTL_RxQ3_Debug
MTL_RxQ3_Control
MTL_RxQ3_Flow_Control
MTL_Q3_Interrupt_Enable
MTL_Q3_Interrupt_Status
0EMAC0_DWCXG_MTL_TCQ4 Address Map
0EMAC0_DWCXG_MTL_TCQ4 Summary
MTL_TxQ4_Operation_Mode
MTL_TxQ4_Underflow
MTL_TxQ4_Debug
MTL_TC4_ETS_Control
MTL_TC4_ETS_Status
MTL_TC4_Quantum_Weight
MTL_RxQ4_Operation_Mode
MTL_RxQ4_Missed_Pkt_Overflow_Cnt
MTL_RxQ4_Debug
MTL_RxQ4_Control
MTL_RxQ4_Flow_Control
MTL_Q4_Interrupt_Enable
MTL_Q4_Interrupt_Status
0EMAC0_DWCXG_MTL_TCQ5 Address Map
0EMAC0_DWCXG_MTL_TCQ5 Summary
MTL_TxQ5_Operation_Mode
MTL_TxQ5_Underflow
MTL_TxQ5_Debug
MTL_TC5_ETS_Control
MTL_TC5_ETS_Status
MTL_TC5_Quantum_Weight
MTL_RxQ5_Operation_Mode
MTL_RxQ5_Missed_Pkt_Overflow_Cnt
MTL_RxQ5_Debug
MTL_RxQ5_Control
MTL_RxQ5_Flow_Control
MTL_Q5_Interrupt_Enable
MTL_Q5_Interrupt_Status
0EMAC0_DWCXG_MTL_TCQ6 Address Map
0EMAC0_DWCXG_MTL_TCQ6 Summary
MTL_TxQ6_Operation_Mode
MTL_TxQ6_Underflow
MTL_TxQ6_Debug
MTL_TC6_ETS_Control
MTL_TC6_ETS_Status
MTL_TC6_Quantum_Weight
MTL_RxQ6_Operation_Mode
MTL_RxQ6_Missed_Pkt_Overflow_Cnt
MTL_RxQ6_Debug
MTL_RxQ6_Control
MTL_RxQ6_Flow_Control
MTL_Q6_Interrupt_Enable
MTL_Q6_Interrupt_Status
0EMAC0_DWCXG_MTL_TCQ7 Address Map
0EMAC0_DWCXG_MTL_TCQ7 Summary
MTL_TxQ7_Operation_Mode
MTL_TxQ7_Underflow
MTL_TxQ7_Debug
MTL_TC7_ETS_Control
MTL_TC7_ETS_Status
MTL_TC7_Quantum_Weight
MTL_TC7_SendSlopeCredit
MTL_TC7_HiCredit
MTL_TC7_LoCredit
MTL_RxQ7_Operation_Mode
MTL_RxQ7_Missed_Pkt_Overflow_Cnt
MTL_RxQ7_Debug
MTL_RxQ7_Control
MTL_RxQ7_Flow_Control
MTL_Q7_Interrupt_Enable
MTL_Q7_Interrupt_Status
0EMAC0_DWCXG_DMA Address Map
0EMAC0_DWCXG_DMA Summary
DMA_Mode
DMA_SysBus_Mode
DMA_Interrupt_Status
AXI_Tx_AR_ACE_Control
AXI_Rx_AW_ACE_Control
AXI_TxRx_AWAR_ACE_Control
DMA_Debug_Status0
DMA_Debug_Status1
DMA_Debug_Status3
DMA_Tx_EDMA_Control
DMA_Rx_EDMA_Control
AXI_LPI_Entry_Interval
DMA_TBS_CTRL0
DMA_TBS_CTRL1
DMA_TBS_CTRL2
DMA_TBS_CTRL3
DMA_CH_Ind_Ctrl
DMA_CH_Ind_Data
0EMAC0_DWCXG_DMA_CH0 Address Map
0EMAC0_DWCXG_DMA_CH0 Summary
DMA_CH0_Control
DMA_CH0_Tx_Control
DMA_CH0_Rx_Control
DMA_CH0_Slot_Function_Control_Status
DMA_CH0_TxDesc_List_HAddress
DMA_CH0_TxDesc_List_LAddress
DMA_CH0_RxDesc_List_HAddress
DMA_CH0_RxDesc_List_LAddress
DMA_CH0_TxDesc_Tail_LPointer
DMA_CH0_RxDesc_Tail_LPointer
DMA_CH0_Tx_Control2
DMA_CH0_Rx_Control2
DMA_CH0_Interrupt_Enable
DMA_CH0_Rx_Interrupt_Watchdog_Timer
DMA_CH0_Current_App_TxDesc_L
DMA_CH0_Current_App_RxDesc_L
DMA_CH0_Current_App_TxBuffer_H
DMA_CH0_Current_App_TxBuffer_L
DMA_CH0_Current_App_RxBuffer_H
DMA_CH0_Current_App_RxBuffer_L
DMA_CH0_Status
DMA_CH0_Debug_Status
DMA_CH0_Desc_Mem_Cache_Fill_Level
DMA_CH0_Miss_Packet_Cnt
DMA_CH0_Tx_Data_Xfer_Ring_Offset
DMA_CH0_Rx_Data_Xfer_Ring_Offset
DMA_CH0_Tx_Desc_Write_Ring_Offset
DMA_CH0_Rx_Desc_Write_Ring_Offset
0EMAC0_DWCXG_DMA_CH1 Address Map
0EMAC0_DWCXG_DMA_CH1 Summary
DMA_CH1_Control
DMA_CH1_Tx_Control
DMA_CH1_Rx_Control
DMA_CH1_Slot_Function_Control_Status
DMA_CH1_TxDesc_List_HAddress
DMA_CH1_TxDesc_List_LAddress
DMA_CH1_RxDesc_List_HAddress
DMA_CH1_RxDesc_List_LAddress
DMA_CH1_TxDesc_Tail_LPointer
DMA_CH1_RxDesc_Tail_LPointer
DMA_CH1_Tx_Control2
DMA_CH1_Rx_Control2
DMA_CH1_Interrupt_Enable
DMA_CH1_Rx_Interrupt_Watchdog_Timer
DMA_CH1_Current_App_TxDesc_L
DMA_CH1_Current_App_RxDesc_L
DMA_CH1_Current_App_TxBuffer_H
DMA_CH1_Current_App_TxBuffer_L
DMA_CH1_Current_App_RxBuffer_H
DMA_CH1_Current_App_RxBuffer_L
DMA_CH1_Status
DMA_CH1_Debug_Status
DMA_CH1_Desc_Mem_Cache_Fill_Level
DMA_CH1_Miss_Packet_Cnt
DMA_CH1_Tx_Data_Xfer_Ring_Offset
DMA_CH1_Rx_Data_Xfer_Ring_Offset
DMA_CH1_Tx_Desc_Write_Ring_Offset
DMA_CH1_Rx_Desc_Write_Ring_Offset
0EMAC0_DWCXG_DMA_CH2 Address Map
0EMAC0_DWCXG_DMA_CH2 Summary
DMA_CH2_Control
DMA_CH2_Tx_Control
DMA_CH2_Rx_Control
DMA_CH2_Slot_Function_Control_Status
DMA_CH2_TxDesc_List_HAddress
DMA_CH2_TxDesc_List_LAddress
DMA_CH2_RxDesc_List_HAddress
DMA_CH2_RxDesc_List_LAddress
DMA_CH2_TxDesc_Tail_LPointer
DMA_CH2_RxDesc_Tail_LPointer
DMA_CH2_Tx_Control2
DMA_CH2_Rx_Control2
DMA_CH2_Interrupt_Enable
DMA_CH2_Rx_Interrupt_Watchdog_Timer
DMA_CH2_Current_App_TxDesc_L
DMA_CH2_Current_App_RxDesc_L
DMA_CH2_Current_App_TxBuffer_H
DMA_CH2_Current_App_TxBuffer_L
DMA_CH2_Current_App_RxBuffer_H
DMA_CH2_Current_App_RxBuffer_L
DMA_CH2_Status
DMA_CH2_Debug_Status
DMA_CH2_Desc_Mem_Cache_Fill_Level
DMA_CH2_Miss_Packet_Cnt
DMA_CH2_Tx_Data_Xfer_Ring_Offset
DMA_CH2_Rx_Data_Xfer_Ring_Offset
DMA_CH2_Tx_Desc_Write_Ring_Offset
DMA_CH2_Rx_Desc_Write_Ring_Offset
0EMAC0_DWCXG_DMA_CH3 Address Map
0EMAC0_DWCXG_DMA_CH3 Summary
DMA_CH3_Control
DMA_CH3_Tx_Control
DMA_CH3_Rx_Control
DMA_CH3_Slot_Function_Control_Status
DMA_CH3_TxDesc_List_HAddress
DMA_CH3_TxDesc_List_LAddress
DMA_CH3_RxDesc_List_HAddress
DMA_CH3_RxDesc_List_LAddress
DMA_CH3_TxDesc_Tail_LPointer
DMA_CH3_RxDesc_Tail_LPointer
DMA_CH3_Tx_Control2
DMA_CH3_Rx_Control2
DMA_CH3_Interrupt_Enable
DMA_CH3_Rx_Interrupt_Watchdog_Timer
DMA_CH3_Current_App_TxDesc_L
DMA_CH3_Current_App_RxDesc_L
DMA_CH3_Current_App_TxBuffer_H
DMA_CH3_Current_App_TxBuffer_L
DMA_CH3_Current_App_RxBuffer_H
DMA_CH3_Current_App_RxBuffer_L
DMA_CH3_Status
DMA_CH3_Debug_Status
DMA_CH3_Desc_Mem_Cache_Fill_Level
DMA_CH3_Miss_Packet_Cnt
DMA_CH3_Tx_Data_Xfer_Ring_Offset
DMA_CH3_Rx_Data_Xfer_Ring_Offset
DMA_CH3_Tx_Desc_Write_Ring_Offset
DMA_CH3_Rx_Desc_Write_Ring_Offset
0EMAC0_DWCXG_DMA_CH4 Address Map
0EMAC0_DWCXG_DMA_CH4 Summary
DMA_CH4_Control
DMA_CH4_Tx_Control
DMA_CH4_Rx_Control
DMA_CH4_Slot_Function_Control_Status
DMA_CH4_TxDesc_List_HAddress
DMA_CH4_TxDesc_List_LAddress
DMA_CH4_RxDesc_List_HAddress
DMA_CH4_RxDesc_List_LAddress
DMA_CH4_TxDesc_Tail_LPointer
DMA_CH4_RxDesc_Tail_LPointer
DMA_CH4_Tx_Control2
DMA_CH4_Rx_Control2
DMA_CH4_Interrupt_Enable
DMA_CH4_Rx_Interrupt_Watchdog_Timer
DMA_CH4_Current_App_TxDesc_L
DMA_CH4_Current_App_RxDesc_L
DMA_CH4_Current_App_TxBuffer_H
DMA_CH4_Current_App_TxBuffer_L
DMA_CH4_Current_App_RxBuffer_H
DMA_CH4_Current_App_RxBuffer_L
DMA_CH4_Status
DMA_CH4_Debug_Status
DMA_CH4_Desc_Mem_Cache_Fill_Level
DMA_CH4_Miss_Packet_Cnt
DMA_CH4_Tx_Data_Xfer_Ring_Offset
DMA_CH4_Rx_Data_Xfer_Ring_Offset
DMA_CH4_Tx_Desc_Write_Ring_Offset
DMA_CH4_Rx_Desc_Write_Ring_Offset
0EMAC0_DWCXG_DMA_CH5 Address Map
0EMAC0_DWCXG_DMA_CH5 Summary
DMA_CH5_Control
DMA_CH5_Tx_Control
DMA_CH5_Rx_Control
DMA_CH5_Slot_Function_Control_Status
DMA_CH5_TxDesc_List_HAddress
DMA_CH5_TxDesc_List_LAddress
DMA_CH5_RxDesc_List_HAddress
DMA_CH5_RxDesc_List_LAddress
DMA_CH5_TxDesc_Tail_LPointer
DMA_CH5_RxDesc_Tail_LPointer
DMA_CH5_Tx_Control2
DMA_CH5_Rx_Control2
DMA_CH5_Interrupt_Enable
DMA_CH5_Rx_Interrupt_Watchdog_Timer
DMA_CH5_Current_App_TxDesc_L
DMA_CH5_Current_App_RxDesc_L
DMA_CH5_Current_App_TxBuffer_H
DMA_CH5_Current_App_TxBuffer_L
DMA_CH5_Current_App_RxBuffer_H
DMA_CH5_Current_App_RxBuffer_L
DMA_CH5_Status
DMA_CH5_Debug_Status
DMA_CH5_Desc_Mem_Cache_Fill_Level
DMA_CH5_Miss_Packet_Cnt
DMA_CH5_Tx_Data_Xfer_Ring_Offset
DMA_CH5_Rx_Data_Xfer_Ring_Offset
DMA_CH5_Tx_Desc_Write_Ring_Offset
DMA_CH5_Rx_Desc_Write_Ring_Offset
0EMAC0_DWCXG_DMA_CH6 Address Map
0EMAC0_DWCXG_DMA_CH6 Summary
DMA_CH6_Control
DMA_CH6_Tx_Control
DMA_CH6_Rx_Control
DMA_CH6_Slot_Function_Control_Status
DMA_CH6_TxDesc_List_HAddress
DMA_CH6_TxDesc_List_LAddress
DMA_CH6_RxDesc_List_HAddress
DMA_CH6_RxDesc_List_LAddress
DMA_CH6_TxDesc_Tail_LPointer
DMA_CH6_RxDesc_Tail_LPointer
DMA_CH6_Tx_Control2
DMA_CH6_Rx_Control2
DMA_CH6_Interrupt_Enable
DMA_CH6_Rx_Interrupt_Watchdog_Timer
DMA_CH6_Current_App_TxDesc_L
DMA_CH6_Current_App_RxDesc_L
DMA_CH6_Current_App_TxBuffer_H
DMA_CH6_Current_App_TxBuffer_L
DMA_CH6_Current_App_RxBuffer_H
DMA_CH6_Current_App_RxBuffer_L
DMA_CH6_Status
DMA_CH6_Debug_Status
DMA_CH6_Desc_Mem_Cache_Fill_Level
DMA_CH6_Miss_Packet_Cnt
DMA_CH6_Tx_Data_Xfer_Ring_Offset
DMA_CH6_Rx_Data_Xfer_Ring_Offset
DMA_CH6_Tx_Desc_Write_Ring_Offset
DMA_CH6_Rx_Desc_Write_Ring_Offset
0EMAC0_DWCXG_DMA_CH7 Address Map
0EMAC0_DWCXG_DMA_CH7 Summary
DMA_CH7_Control
DMA_CH7_Tx_Control
DMA_CH7_Rx_Control
DMA_CH7_Slot_Function_Control_Status
DMA_CH7_TxDesc_List_HAddress
DMA_CH7_TxDesc_List_LAddress
DMA_CH7_RxDesc_List_HAddress
DMA_CH7_RxDesc_List_LAddress
DMA_CH7_TxDesc_Tail_LPointer
DMA_CH7_RxDesc_Tail_LPointer
DMA_CH7_Tx_Control2
DMA_CH7_Rx_Control2
DMA_CH7_Interrupt_Enable
DMA_CH7_Rx_Interrupt_Watchdog_Timer
DMA_CH7_Current_App_TxDesc_L
DMA_CH7_Current_App_RxDesc_L
DMA_CH7_Current_App_TxBuffer_H
DMA_CH7_Current_App_TxBuffer_L
DMA_CH7_Current_App_RxBuffer_H
DMA_CH7_Current_App_RxBuffer_L
DMA_CH7_Status
DMA_CH7_Debug_Status
DMA_CH7_Desc_Mem_Cache_Fill_Level
DMA_CH7_Miss_Packet_Cnt
DMA_CH7_Tx_Data_Xfer_Ring_Offset
DMA_CH7_Rx_Data_Xfer_Ring_Offset
DMA_CH7_Tx_Desc_Write_Ring_Offset
DMA_CH7_Rx_Desc_Write_Ring_Offset
EMAC1 Address Block Group
1EMAC1_DWCXG_CORE Address Map
1EMAC1_DWCXG_CORE Summary
MAC_Tx_Configuration
MAC_Rx_Configuration
MAC_Packet_Filter
MAC_WD_JB_Timeout
MAC_Hash_Table_Reg0
MAC_Hash_Table_Reg1
MAC_VLAN_Tag_Ctrl
MAC_VLAN_Tag_Data
MAC_VLAN_Hash_Table
MAC_VLAN_Incl
MAC_Inner_VLAN_Incl
MAC_Rx_Eth_Type_Match
MAC_Q0_Tx_Flow_Ctrl
MAC_Q1_Tx_Flow_Ctrl
MAC_Q2_Tx_Flow_Ctrl
MAC_Q3_Tx_Flow_Ctrl
MAC_Q4_Tx_Flow_Ctrl
MAC_Q5_Tx_Flow_Ctrl
MAC_Q6_Tx_Flow_Ctrl
MAC_Q7_Tx_Flow_Ctrl
MAC_Rx_Flow_Ctrl
MAC_RxQ_Ctrl4
MAC_RxQ_Ctrl5
MAC_RxQ_Ctrl0
MAC_RxQ_Ctrl1
MAC_RxQ_Ctrl2
MAC_RxQ_Ctrl3
MAC_Interrupt_Status
MAC_Interrupt_Enable
MAC_Rx_Tx_Status
MAC_Version
MAC_Debug
MAC_HW_Feature0
MAC_HW_Feature1
MAC_HW_Feature2
MAC_HW_Feature3
MAC_HW_Feature4
MAC_Extended_Configuration
MAC_Ext_Cfg1
MDIO_Single_Command_Address
MDIO_Single_Command_Control_Data
MDIO_Continuous_Write_Address
MDIO_Continuous_Write_Data
MDIO_Continuous_Scan_Port_Enable
MDIO_Interrupt_Status
MDIO_Interrupt_Enable
MDIO_Port_Connect_Disconnect_Status
MDIO_Clause_22_Port
MDIO_Port_Nx4_Indirect_Control
MDIO_PortNx4P0_Device_In_Use
MDIO_PortNx4P0_Link_Status
MDIO_PortNx4P0_Alive_Status
MDIO_PortNx4P1_Device_In_Use
MDIO_PortNx4P1_Link_Status
MDIO_PortNx4P1_Alive_Status
MDIO_PortNx4P2_Device_In_Use
MDIO_PortNx4P2_Link_Status
MDIO_PortNx4P2_Alive_Status
MDIO_PortNx4P3_Device_In_Use
MDIO_PortNx4P3_Link_Status
MDIO_PortNx4P3_Alive_Status
MAC_GPIO_Control
MAC_GPIO_Status
MAC_FPE_CTRL_STS
MAC_CSR_SW_Ctrl
MAC_Address0_High
MAC_Address0_Low
MAC_Address1_High
MAC_Address1_Low
MAC_Address2_High
MAC_Address2_Low
MAC_Address3_High
MAC_Address3_Low
MAC_Address4_High
MAC_Address4_Low
MAC_Address5_High
MAC_Address5_Low
MAC_Address6_High
MAC_Address6_Low
MAC_Address7_High
MAC_Address7_Low
MAC_Address8_High
MAC_Address8_Low
MAC_Address9_High
MAC_Address9_Low
MAC_Address10_High
MAC_Address10_Low
MAC_Address11_High
MAC_Address11_Low
MAC_Address12_High
MAC_Address12_Low
MAC_Address13_High
MAC_Address13_Low
MAC_Address14_High
MAC_Address14_Low
MAC_Address15_High
MAC_Address15_Low
MAC_Address16_High
MAC_Address16_Low
MAC_Address17_High
MAC_Address17_Low
MAC_Address18_High
MAC_Address18_Low
MAC_Address19_High
MAC_Address19_Low
MAC_Address20_High
MAC_Address20_Low
MAC_Address21_High
MAC_Address21_Low
MAC_Address22_High
MAC_Address22_Low
MAC_Address23_High
MAC_Address23_Low
MAC_Address24_High
MAC_Address24_Low
MAC_Address25_High
MAC_Address25_Low
MAC_Address26_High
MAC_Address26_Low
MAC_Address27_High
MAC_Address27_Low
MAC_Address28_High
MAC_Address28_Low
MAC_Address29_High
MAC_Address29_Low
MAC_Address30_High
MAC_Address30_Low
MAC_Address31_High
MAC_Address31_Low
MAC_Indir_Access_Ctrl
MAC_Indir_Access_Data
MMC_Control
MMC_Rx_Interrupt
MMC_Tx_Interrupt
MMC_Receive_Interrupt_Enable
MMC_Transmit_Interrupt_Enable
Tx_Octet_Count_Good_Bad_Low
Tx_Octet_Count_Good_Bad_High
Tx_Packet_Count_Good_Bad_Low
Tx_Broadcast_Packets_Good_Low
Tx_Multicast_Packets_Good_Low
Tx_64Octets_Packets_Good_Bad_Low
Tx_65To127Octets_Packets_Good_Bad_Low
Tx_128To255Octets_Packets_Good_Bad_Low
Tx_256To511Octets_Packets_Good_Bad_Low
Tx_512To1023Octets_Packets_Good_Bad_Low
Tx_1024ToMaxOctets_Packets_Good_Bad_Low
Tx_Unicast_Packets_Good_Bad_Low
Tx_Multicast_Packets_Good_Bad_Low
Tx_Broadcast_Packets_Good_Bad_Low
Tx_Underflow_Error_Packets_Low
Tx_Octet_Count_Good_Low
Tx_Octet_Count_Good_High
Tx_Packet_Count_Good_Low
Tx_Pause_Packets_Low
Tx_VLAN_Packets_Good_Low
Rx_Packet_Count_Good_Bad_Low
Rx_Octet_Count_Good_Bad_Low
Rx_Octet_Count_Good_Bad_High
Rx_Octet_Count_Good_Low
Rx_Octet_Count_Good_High
Rx_Broadcast_Packets_Good_Low
Rx_Multicast_Packets_Good_Low
Rx_CRC_Error_Packets_Low
Rx_Runt_Error_Packets
Rx_Jabber_Error_Packets
Rx_Undersize_Packets_Good
Rx_Oversize_Packets_Good
Rx_64Octets_Packets_Good_Bad_Low
Rx_65To127Octets_Packets_Good_Bad_Low
Rx_128To255Octets_Packets_Good_Bad_Low
Rx_256To511Octets_Packets_Good_Bad_Low
Rx_512To1023Octets_Packets_Good_Bad_Low
Rx_1024ToMaxOctets_Packets_Good_Bad_Low
Rx_Unicast_Packets_Good_Low
Rx_Length_Error_Packets_Low
Rx_OutofRange_Packets_Low
Rx_Pause_Packets_Low
Rx_FIFOOverflow_Packets_Low
Rx_VLAN_Packets_Good_Bad_Low
Rx_Watchdog_Error_Packets
Rx_Discard_Packets_Good_Bad_Low
Rx_Discard_Octets_Good_Bad_Low
Rx_Discard_Octets_Good_Bad_High
Rx_Alignment_Error_Packets
MMC_FPE_Tx_Interrupt
MMC_FPE_Tx_Interrupt_Mask
MMC_Tx_FPE_Fragment_Cntr
MMC_Tx_Hold_Req_Cntr
MMC_Tx_Gate_Orun_Cntr_Low
MMC_Tx_Gate_Orun_Cntr_High
MMC_FPE_Rx_Interrupt
MMC_FPE_Rx_Interrupt_Mask
MMC_Rx_Packet_Assembly_Err_Cntr
MMC_Rx_Packet_SMD_Err_Cntr
MMC_Rx_Packet_Assembly_OK_Cntr
MMC_Rx_FPE_Fragment_Cntr
Tx_Single_Collision_Good_Packets
Tx_Multiple_Collision_Good_Packets
Tx_Deferred_Packets
Tx_Late_Collision_Packets
Tx_Excessive_Collision_Packets
Tx_Carrier_Error_Packets
Tx_Excessive_Deferral_Error
MMC_IPC_Rx_Interrupt_Mask
MMC_IPC_Rx_Interrupt
RxIPv4_Good_Packets_Low
RxIPv4_Header_Error_Packets_Low
RxIPv4_No_Payload_Packets_Low
RxIPv4_Fragmented_Packets_Low
RxIPv4_UDP_Checksum_Disabled_Packets_Low
RxIPv6_Good_Packets_Low
RxIPv6_Header_Error_Packets_Low
RxIPv6_No_Payload_Packets_Low
RxUDP_Good_Packets_Low
RxUDP_Error_Packets_Low
RxTCP_Good_Packets_Low
RxTCP_Error_Packets_Low
RxICMP_Good_Packets_Low
RxICMP_Error_Packets_Low
RxIPv4_Good_Octets_Low
RxIPv4_Header_Error_Octets_Low
RxIPv4_No_Payload_Octets_Low
RxIPv4_Fragmented_Octets_Low
RxIPv4_UDP_Checksum_Disable_Octets_Low
RxIPv6_Good_Octets_Low
RxIPv6_Header_Error_Octets_Low
RxIPv6_No_Payload_Octets_Low
RxUDP_Good_Octets_Low
RxUDP_Error_Octets_Low
RxTCP_Good_Octets_Low
RxTCP_Error_Octets_Low
RxICMP_Good_Octets_Low
RxICMP_Error_Octets_Low
MAC_L3_L4_Address_Control
MAC_L3_L4_Data
MAC_ARP_Address
MAC_Timestamp_Control
MAC_Sub_Second_Increment
MAC_System_Time_Seconds
MAC_System_Time_Nanoseconds
MAC_System_Time_Seconds_Update
MAC_System_Time_Nanoseconds_Update
MAC_Timestamp_Addend
MAC_System_Time_Higher_Word_Seconds
MAC_Timestamp_Status
MAC_Tx_Timestamp_Status_Nanoseconds
MAC_Tx_Timestamp_Status_Seconds
MAC_Tx_Timestamp_Status_PktID
MAC_Auxiliary_Control
MAC_Auxiliary_Timestamp_Nanoseconds
MAC_Auxiliary_Timestamp_Seconds
MAC_Timestamp_Ingress_Asym_Corr
MAC_Timestamp_Egress_Asym_Corr
MAC_Timestamp_Ingress_Corr_Nanosecond
MAC_Timestamp_Ingress_Corr_Subnanosecond
MAC_Timestamp_Egress_Corr_Nanosecond
MAC_Timestamp_Egress_Corr_Subnanosecond
MAC_PPS_Control
MAC_PPS0_Target_Time_Seconds
MAC_PPS0_Target_Time_Nanoseconds
MAC_PPS0_Interval
MAC_PPS0_Width
MAC_PPS1_Target_Time_Seconds
MAC_PPS1_Target_Time_Nanoseconds
MAC_PPS1_Interval
MAC_PPS1_Width
MAC_PTO_Control
MAC_Source_Port_Identity0
MAC_Source_Port_Identity1
MAC_Source_Port_Identity2
MAC_Log_Message_Interval
1EMAC1_DWCXG_MTL Address Map
1EMAC1_DWCXG_MTL Summary
MTL_Operation_Mode
MTL_Debug_Control
MTL_Debug_Status
MTL_FIFO_Debug_Data
MTL_Interrupt_Status
MTL_RxQ_DMA_Map0
MTL_RxQ_DMA_Map1
MTL_TC_Prty_Map0
MTL_TC_Prty_Map1
MTL_TBS_CTRL
MTL_TBS_STATS
MTL_EST_Control
MTL_EST_Overhead
MTL_EST_Status
MTL_EST_Sch_Error
MTL_EST_Frm_Size_Error
MTL_EST_Frm_Size_Capture
MTL_EST_Intr_Enable
MTL_GCL_Control
MTL_GCL_Data
MTL_FPE_CTRL_STS
MTL_FPE_Advance
1EMAC1_DWCXG_MTL_TCQ0 Address Map
1EMAC1_DWCXG_MTL_TCQ0 Summary
MTL_TxQ0_Operation_Mode
MTL_TxQ0_Underflow
MTL_TxQ0_Debug
MTL_TC0_ETS_Control
MTL_TC0_ETS_Status
MTL_TC0_Quantum_Weight
MTL_RxQ0_Operation_Mode
MTL_RxQ0_Missed_Pkt_Overflow_Cnt
MTL_RxQ0_Debug
MTL_RxQ0_Control
MTL_RxQ0_Flow_Control
MTL_Q0_Interrupt_Enable
MTL_Q0_Interrupt_Status
1EMAC1_DWCXG_MTL_TCQ1 Address Map
1EMAC1_DWCXG_MTL_TCQ1 Summary
MTL_TxQ1_Operation_Mode
MTL_TxQ1_Underflow
MTL_TxQ1_Debug
MTL_TC1_ETS_Control
MTL_TC1_ETS_Status
MTL_TC1_Quantum_Weight
MTL_RxQ1_Operation_Mode
MTL_RxQ1_Missed_Pkt_Overflow_Cnt
MTL_RxQ1_Debug
MTL_RxQ1_Control
MTL_RxQ1_Flow_Control
MTL_Q1_Interrupt_Enable
MTL_Q1_Interrupt_Status
1EMAC1_DWCXG_MTL_TCQ2 Address Map
1EMAC1_DWCXG_MTL_TCQ2 Summary
MTL_TxQ2_Operation_Mode
MTL_TxQ2_Underflow
MTL_TxQ2_Debug
MTL_TC2_ETS_Control
MTL_TC2_ETS_Status
MTL_TC2_Quantum_Weight
MTL_RxQ2_Operation_Mode
MTL_RxQ2_Missed_Pkt_Overflow_Cnt
MTL_RxQ2_Debug
MTL_RxQ2_Control
MTL_RxQ2_Flow_Control
MTL_Q2_Interrupt_Enable
MTL_Q2_Interrupt_Status
1EMAC1_DWCXG_MTL_TCQ3 Address Map
1EMAC1_DWCXG_MTL_TCQ3 Summary
MTL_TxQ3_Operation_Mode
MTL_TxQ3_Underflow
MTL_TxQ3_Debug
MTL_TC3_ETS_Control
MTL_TC3_ETS_Status
MTL_TC3_Quantum_Weight
MTL_RxQ3_Operation_Mode
MTL_RxQ3_Missed_Pkt_Overflow_Cnt
MTL_RxQ3_Debug
MTL_RxQ3_Control
MTL_RxQ3_Flow_Control
MTL_Q3_Interrupt_Enable
MTL_Q3_Interrupt_Status
1EMAC1_DWCXG_MTL_TCQ4 Address Map
1EMAC1_DWCXG_MTL_TCQ4 Summary
MTL_TxQ4_Operation_Mode
MTL_TxQ4_Underflow
MTL_TxQ4_Debug
MTL_TC4_ETS_Control
MTL_TC4_ETS_Status
MTL_TC4_Quantum_Weight
MTL_RxQ4_Operation_Mode
MTL_RxQ4_Missed_Pkt_Overflow_Cnt
MTL_RxQ4_Debug
MTL_RxQ4_Control
MTL_RxQ4_Flow_Control
MTL_Q4_Interrupt_Enable
MTL_Q4_Interrupt_Status
1EMAC1_DWCXG_MTL_TCQ5 Address Map
1EMAC1_DWCXG_MTL_TCQ5 Summary
MTL_TxQ5_Operation_Mode
MTL_TxQ5_Underflow
MTL_TxQ5_Debug
MTL_TC5_ETS_Control
MTL_TC5_ETS_Status
MTL_TC5_Quantum_Weight
MTL_RxQ5_Operation_Mode
MTL_RxQ5_Missed_Pkt_Overflow_Cnt
MTL_RxQ5_Debug
MTL_RxQ5_Control
MTL_RxQ5_Flow_Control
MTL_Q5_Interrupt_Enable
MTL_Q5_Interrupt_Status
1EMAC1_DWCXG_MTL_TCQ6 Address Map
1EMAC1_DWCXG_MTL_TCQ6 Summary
MTL_TxQ6_Operation_Mode
MTL_TxQ6_Underflow
MTL_TxQ6_Debug
MTL_TC6_ETS_Control
MTL_TC6_ETS_Status
MTL_TC6_Quantum_Weight
MTL_RxQ6_Operation_Mode
MTL_RxQ6_Missed_Pkt_Overflow_Cnt
MTL_RxQ6_Debug
MTL_RxQ6_Control
MTL_RxQ6_Flow_Control
MTL_Q6_Interrupt_Enable
MTL_Q6_Interrupt_Status
1EMAC1_DWCXG_MTL_TCQ7 Address Map
1EMAC1_DWCXG_MTL_TCQ7 Summary
MTL_TxQ7_Operation_Mode
MTL_TxQ7_Underflow
MTL_TxQ7_Debug
MTL_TC7_ETS_Control
MTL_TC7_ETS_Status
MTL_TC7_Quantum_Weight
MTL_TC7_SendSlopeCredit
MTL_TC7_HiCredit
MTL_TC7_LoCredit
MTL_RxQ7_Operation_Mode
MTL_RxQ7_Missed_Pkt_Overflow_Cnt
MTL_RxQ7_Debug
MTL_RxQ7_Control
MTL_RxQ7_Flow_Control
MTL_Q7_Interrupt_Enable
MTL_Q7_Interrupt_Status
1EMAC1_DWCXG_DMA Address Map
1EMAC1_DWCXG_DMA Summary
DMA_Mode
DMA_SysBus_Mode
DMA_Interrupt_Status
AXI_Tx_AR_ACE_Control
AXI_Rx_AW_ACE_Control
AXI_TxRx_AWAR_ACE_Control
DMA_Debug_Status0
DMA_Debug_Status1
DMA_Debug_Status3
DMA_Tx_EDMA_Control
DMA_Rx_EDMA_Control
AXI_LPI_Entry_Interval
DMA_TBS_CTRL0
DMA_TBS_CTRL1
DMA_TBS_CTRL2
DMA_TBS_CTRL3
DMA_CH_Ind_Ctrl
DMA_CH_Ind_Data
1EMAC1_DWCXG_DMA_CH0 Address Map
1EMAC1_DWCXG_DMA_CH0 Summary
DMA_CH0_Control
DMA_CH0_Tx_Control
DMA_CH0_Rx_Control
DMA_CH0_Slot_Function_Control_Status
DMA_CH0_TxDesc_List_HAddress
DMA_CH0_TxDesc_List_LAddress
DMA_CH0_RxDesc_List_HAddress
DMA_CH0_RxDesc_List_LAddress
DMA_CH0_TxDesc_Tail_LPointer
DMA_CH0_RxDesc_Tail_LPointer
DMA_CH0_Tx_Control2
DMA_CH0_Rx_Control2
DMA_CH0_Interrupt_Enable
DMA_CH0_Rx_Interrupt_Watchdog_Timer
DMA_CH0_Current_App_TxDesc_L
DMA_CH0_Current_App_RxDesc_L
DMA_CH0_Current_App_TxBuffer_H
DMA_CH0_Current_App_TxBuffer_L
DMA_CH0_Current_App_RxBuffer_H
DMA_CH0_Current_App_RxBuffer_L
DMA_CH0_Status
DMA_CH0_Debug_Status
DMA_CH0_Desc_Mem_Cache_Fill_Level
DMA_CH0_Miss_Packet_Cnt
DMA_CH0_Tx_Data_Xfer_Ring_Offset
DMA_CH0_Rx_Data_Xfer_Ring_Offset
DMA_CH0_Tx_Desc_Write_Ring_Offset
DMA_CH0_Rx_Desc_Write_Ring_Offset
1EMAC1_DWCXG_DMA_CH1 Address Map
1EMAC1_DWCXG_DMA_CH1 Summary
DMA_CH1_Control
DMA_CH1_Tx_Control
DMA_CH1_Rx_Control
DMA_CH1_Slot_Function_Control_Status
DMA_CH1_TxDesc_List_HAddress
DMA_CH1_TxDesc_List_LAddress
DMA_CH1_RxDesc_List_HAddress
DMA_CH1_RxDesc_List_LAddress
DMA_CH1_TxDesc_Tail_LPointer
DMA_CH1_RxDesc_Tail_LPointer
DMA_CH1_Tx_Control2
DMA_CH1_Rx_Control2
DMA_CH1_Interrupt_Enable
DMA_CH1_Rx_Interrupt_Watchdog_Timer
DMA_CH1_Current_App_TxDesc_L
DMA_CH1_Current_App_RxDesc_L
DMA_CH1_Current_App_TxBuffer_H
DMA_CH1_Current_App_TxBuffer_L
DMA_CH1_Current_App_RxBuffer_H
DMA_CH1_Current_App_RxBuffer_L
DMA_CH1_Status
DMA_CH1_Debug_Status
DMA_CH1_Desc_Mem_Cache_Fill_Level
DMA_CH1_Miss_Packet_Cnt
DMA_CH1_Tx_Data_Xfer_Ring_Offset
DMA_CH1_Rx_Data_Xfer_Ring_Offset
DMA_CH1_Tx_Desc_Write_Ring_Offset
DMA_CH1_Rx_Desc_Write_Ring_Offset
1EMAC1_DWCXG_DMA_CH2 Address Map
1EMAC1_DWCXG_DMA_CH2 Summary
DMA_CH2_Control
DMA_CH2_Tx_Control
DMA_CH2_Rx_Control
DMA_CH2_Slot_Function_Control_Status
DMA_CH2_TxDesc_List_HAddress
DMA_CH2_TxDesc_List_LAddress
DMA_CH2_RxDesc_List_HAddress
DMA_CH2_RxDesc_List_LAddress
DMA_CH2_TxDesc_Tail_LPointer
DMA_CH2_RxDesc_Tail_LPointer
DMA_CH2_Tx_Control2
DMA_CH2_Rx_Control2
DMA_CH2_Interrupt_Enable
DMA_CH2_Rx_Interrupt_Watchdog_Timer
DMA_CH2_Current_App_TxDesc_L
DMA_CH2_Current_App_RxDesc_L
DMA_CH2_Current_App_TxBuffer_H
DMA_CH2_Current_App_TxBuffer_L
DMA_CH2_Current_App_RxBuffer_H
DMA_CH2_Current_App_RxBuffer_L
DMA_CH2_Status
DMA_CH2_Debug_Status
DMA_CH2_Desc_Mem_Cache_Fill_Level
DMA_CH2_Miss_Packet_Cnt
DMA_CH2_Tx_Data_Xfer_Ring_Offset
DMA_CH2_Rx_Data_Xfer_Ring_Offset
DMA_CH2_Tx_Desc_Write_Ring_Offset
DMA_CH2_Rx_Desc_Write_Ring_Offset
1EMAC1_DWCXG_DMA_CH3 Address Map
1EMAC1_DWCXG_DMA_CH3 Summary
DMA_CH3_Control
DMA_CH3_Tx_Control
DMA_CH3_Rx_Control
DMA_CH3_Slot_Function_Control_Status
DMA_CH3_TxDesc_List_HAddress
DMA_CH3_TxDesc_List_LAddress
DMA_CH3_RxDesc_List_HAddress
DMA_CH3_RxDesc_List_LAddress
DMA_CH3_TxDesc_Tail_LPointer
DMA_CH3_RxDesc_Tail_LPointer
DMA_CH3_Tx_Control2
DMA_CH3_Rx_Control2
DMA_CH3_Interrupt_Enable
DMA_CH3_Rx_Interrupt_Watchdog_Timer
DMA_CH3_Current_App_TxDesc_L
DMA_CH3_Current_App_RxDesc_L
DMA_CH3_Current_App_TxBuffer_H
DMA_CH3_Current_App_TxBuffer_L
DMA_CH3_Current_App_RxBuffer_H
DMA_CH3_Current_App_RxBuffer_L
DMA_CH3_Status
DMA_CH3_Debug_Status
DMA_CH3_Desc_Mem_Cache_Fill_Level
DMA_CH3_Miss_Packet_Cnt
DMA_CH3_Tx_Data_Xfer_Ring_Offset
DMA_CH3_Rx_Data_Xfer_Ring_Offset
DMA_CH3_Tx_Desc_Write_Ring_Offset
DMA_CH3_Rx_Desc_Write_Ring_Offset
1EMAC1_DWCXG_DMA_CH4 Address Map
1EMAC1_DWCXG_DMA_CH4 Summary
DMA_CH4_Control
DMA_CH4_Tx_Control
DMA_CH4_Rx_Control
DMA_CH4_Slot_Function_Control_Status
DMA_CH4_TxDesc_List_HAddress
DMA_CH4_TxDesc_List_LAddress
DMA_CH4_RxDesc_List_HAddress
DMA_CH4_RxDesc_List_LAddress
DMA_CH4_TxDesc_Tail_LPointer
DMA_CH4_RxDesc_Tail_LPointer
DMA_CH4_Tx_Control2
DMA_CH4_Rx_Control2
DMA_CH4_Interrupt_Enable
DMA_CH4_Rx_Interrupt_Watchdog_Timer
DMA_CH4_Current_App_TxDesc_L
DMA_CH4_Current_App_RxDesc_L
DMA_CH4_Current_App_TxBuffer_H
DMA_CH4_Current_App_TxBuffer_L
DMA_CH4_Current_App_RxBuffer_H
DMA_CH4_Current_App_RxBuffer_L
DMA_CH4_Status
DMA_CH4_Debug_Status
DMA_CH4_Desc_Mem_Cache_Fill_Level
DMA_CH4_Miss_Packet_Cnt
DMA_CH4_Tx_Data_Xfer_Ring_Offset
DMA_CH4_Rx_Data_Xfer_Ring_Offset
DMA_CH4_Tx_Desc_Write_Ring_Offset
DMA_CH4_Rx_Desc_Write_Ring_Offset
1EMAC1_DWCXG_DMA_CH5 Address Map
1EMAC1_DWCXG_DMA_CH5 Summary
DMA_CH5_Control
DMA_CH5_Tx_Control
DMA_CH5_Rx_Control
DMA_CH5_Slot_Function_Control_Status
DMA_CH5_TxDesc_List_HAddress
DMA_CH5_TxDesc_List_LAddress
DMA_CH5_RxDesc_List_HAddress
DMA_CH5_RxDesc_List_LAddress
DMA_CH5_TxDesc_Tail_LPointer
DMA_CH5_RxDesc_Tail_LPointer
DMA_CH5_Tx_Control2
DMA_CH5_Rx_Control2
DMA_CH5_Interrupt_Enable
DMA_CH5_Rx_Interrupt_Watchdog_Timer
DMA_CH5_Current_App_TxDesc_L
DMA_CH5_Current_App_RxDesc_L
DMA_CH5_Current_App_TxBuffer_H
DMA_CH5_Current_App_TxBuffer_L
DMA_CH5_Current_App_RxBuffer_H
DMA_CH5_Current_App_RxBuffer_L
DMA_CH5_Status
DMA_CH5_Debug_Status
DMA_CH5_Desc_Mem_Cache_Fill_Level
DMA_CH5_Miss_Packet_Cnt
DMA_CH5_Tx_Data_Xfer_Ring_Offset
DMA_CH5_Rx_Data_Xfer_Ring_Offset
DMA_CH5_Tx_Desc_Write_Ring_Offset
DMA_CH5_Rx_Desc_Write_Ring_Offset
1EMAC1_DWCXG_DMA_CH6 Address Map
1EMAC1_DWCXG_DMA_CH6 Summary
DMA_CH6_Control
DMA_CH6_Tx_Control
DMA_CH6_Rx_Control
DMA_CH6_Slot_Function_Control_Status
DMA_CH6_TxDesc_List_HAddress
DMA_CH6_TxDesc_List_LAddress
DMA_CH6_RxDesc_List_HAddress
DMA_CH6_RxDesc_List_LAddress
DMA_CH6_TxDesc_Tail_LPointer
DMA_CH6_RxDesc_Tail_LPointer
DMA_CH6_Tx_Control2
DMA_CH6_Rx_Control2
DMA_CH6_Interrupt_Enable
DMA_CH6_Rx_Interrupt_Watchdog_Timer
DMA_CH6_Current_App_TxDesc_L
DMA_CH6_Current_App_RxDesc_L
DMA_CH6_Current_App_TxBuffer_H
DMA_CH6_Current_App_TxBuffer_L
DMA_CH6_Current_App_RxBuffer_H
DMA_CH6_Current_App_RxBuffer_L
DMA_CH6_Status
DMA_CH6_Debug_Status
DMA_CH6_Desc_Mem_Cache_Fill_Level
DMA_CH6_Miss_Packet_Cnt
DMA_CH6_Tx_Data_Xfer_Ring_Offset
DMA_CH6_Rx_Data_Xfer_Ring_Offset
DMA_CH6_Tx_Desc_Write_Ring_Offset
DMA_CH6_Rx_Desc_Write_Ring_Offset
1EMAC1_DWCXG_DMA_CH7 Address Map
1EMAC1_DWCXG_DMA_CH7 Summary
DMA_CH7_Control
DMA_CH7_Tx_Control
DMA_CH7_Rx_Control
DMA_CH7_Slot_Function_Control_Status
DMA_CH7_TxDesc_List_HAddress
DMA_CH7_TxDesc_List_LAddress
DMA_CH7_RxDesc_List_HAddress
DMA_CH7_RxDesc_List_LAddress
DMA_CH7_TxDesc_Tail_LPointer
DMA_CH7_RxDesc_Tail_LPointer
DMA_CH7_Tx_Control2
DMA_CH7_Rx_Control2
DMA_CH7_Interrupt_Enable
DMA_CH7_Rx_Interrupt_Watchdog_Timer
DMA_CH7_Current_App_TxDesc_L
DMA_CH7_Current_App_RxDesc_L
DMA_CH7_Current_App_TxBuffer_H
DMA_CH7_Current_App_TxBuffer_L
DMA_CH7_Current_App_RxBuffer_H
DMA_CH7_Current_App_RxBuffer_L
DMA_CH7_Status
DMA_CH7_Debug_Status
DMA_CH7_Desc_Mem_Cache_Fill_Level
DMA_CH7_Miss_Packet_Cnt
DMA_CH7_Tx_Data_Xfer_Ring_Offset
DMA_CH7_Rx_Data_Xfer_Ring_Offset
DMA_CH7_Tx_Desc_Write_Ring_Offset
DMA_CH7_Rx_Desc_Write_Ring_Offset
EMAC2 Address Block Group
2EMAC2_DWCXG_CORE Address Map
2EMAC2_DWCXG_CORE Summary
MAC_Tx_Configuration
MAC_Rx_Configuration
MAC_Packet_Filter
MAC_WD_JB_Timeout
MAC_Hash_Table_Reg0
MAC_Hash_Table_Reg1
MAC_VLAN_Tag_Ctrl
MAC_VLAN_Tag_Data
MAC_VLAN_Hash_Table
MAC_VLAN_Incl
MAC_Inner_VLAN_Incl
MAC_Rx_Eth_Type_Match
MAC_Q0_Tx_Flow_Ctrl
MAC_Q1_Tx_Flow_Ctrl
MAC_Q2_Tx_Flow_Ctrl
MAC_Q3_Tx_Flow_Ctrl
MAC_Q4_Tx_Flow_Ctrl
MAC_Q5_Tx_Flow_Ctrl
MAC_Q6_Tx_Flow_Ctrl
MAC_Q7_Tx_Flow_Ctrl
MAC_Rx_Flow_Ctrl
MAC_RxQ_Ctrl4
MAC_RxQ_Ctrl5
MAC_RxQ_Ctrl0
MAC_RxQ_Ctrl1
MAC_RxQ_Ctrl2
MAC_RxQ_Ctrl3
MAC_Interrupt_Status
MAC_Interrupt_Enable
MAC_Rx_Tx_Status
MAC_Version
MAC_Debug
MAC_HW_Feature0
MAC_HW_Feature1
MAC_HW_Feature2
MAC_HW_Feature3
MAC_HW_Feature4
MAC_Extended_Configuration
MAC_Ext_Cfg1
MDIO_Single_Command_Address
MDIO_Single_Command_Control_Data
MDIO_Continuous_Write_Address
MDIO_Continuous_Write_Data
MDIO_Continuous_Scan_Port_Enable
MDIO_Interrupt_Status
MDIO_Interrupt_Enable
MDIO_Port_Connect_Disconnect_Status
MDIO_Clause_22_Port
MDIO_Port_Nx4_Indirect_Control
MDIO_PortNx4P0_Device_In_Use
MDIO_PortNx4P0_Link_Status
MDIO_PortNx4P0_Alive_Status
MDIO_PortNx4P1_Device_In_Use
MDIO_PortNx4P1_Link_Status
MDIO_PortNx4P1_Alive_Status
MDIO_PortNx4P2_Device_In_Use
MDIO_PortNx4P2_Link_Status
MDIO_PortNx4P2_Alive_Status
MDIO_PortNx4P3_Device_In_Use
MDIO_PortNx4P3_Link_Status
MDIO_PortNx4P3_Alive_Status
MAC_GPIO_Control
MAC_GPIO_Status
MAC_FPE_CTRL_STS
MAC_CSR_SW_Ctrl
MAC_Address0_High
MAC_Address0_Low
MAC_Address1_High
MAC_Address1_Low
MAC_Address2_High
MAC_Address2_Low
MAC_Address3_High
MAC_Address3_Low
MAC_Address4_High
MAC_Address4_Low
MAC_Address5_High
MAC_Address5_Low
MAC_Address6_High
MAC_Address6_Low
MAC_Address7_High
MAC_Address7_Low
MAC_Address8_High
MAC_Address8_Low
MAC_Address9_High
MAC_Address9_Low
MAC_Address10_High
MAC_Address10_Low
MAC_Address11_High
MAC_Address11_Low
MAC_Address12_High
MAC_Address12_Low
MAC_Address13_High
MAC_Address13_Low
MAC_Address14_High
MAC_Address14_Low
MAC_Address15_High
MAC_Address15_Low
MAC_Address16_High
MAC_Address16_Low
MAC_Address17_High
MAC_Address17_Low
MAC_Address18_High
MAC_Address18_Low
MAC_Address19_High
MAC_Address19_Low
MAC_Address20_High
MAC_Address20_Low
MAC_Address21_High
MAC_Address21_Low
MAC_Address22_High
MAC_Address22_Low
MAC_Address23_High
MAC_Address23_Low
MAC_Address24_High
MAC_Address24_Low
MAC_Address25_High
MAC_Address25_Low
MAC_Address26_High
MAC_Address26_Low
MAC_Address27_High
MAC_Address27_Low
MAC_Address28_High
MAC_Address28_Low
MAC_Address29_High
MAC_Address29_Low
MAC_Address30_High
MAC_Address30_Low
MAC_Address31_High
MAC_Address31_Low
MAC_Indir_Access_Ctrl
MAC_Indir_Access_Data
MMC_Control
MMC_Rx_Interrupt
MMC_Tx_Interrupt
MMC_Receive_Interrupt_Enable
MMC_Transmit_Interrupt_Enable
Tx_Octet_Count_Good_Bad_Low
Tx_Octet_Count_Good_Bad_High
Tx_Packet_Count_Good_Bad_Low
Tx_Broadcast_Packets_Good_Low
Tx_Multicast_Packets_Good_Low
Tx_64Octets_Packets_Good_Bad_Low
Tx_65To127Octets_Packets_Good_Bad_Low
Tx_128To255Octets_Packets_Good_Bad_Low
Tx_256To511Octets_Packets_Good_Bad_Low
Tx_512To1023Octets_Packets_Good_Bad_Low
Tx_1024ToMaxOctets_Packets_Good_Bad_Low
Tx_Unicast_Packets_Good_Bad_Low
Tx_Multicast_Packets_Good_Bad_Low
Tx_Broadcast_Packets_Good_Bad_Low
Tx_Underflow_Error_Packets_Low
Tx_Octet_Count_Good_Low
Tx_Octet_Count_Good_High
Tx_Packet_Count_Good_Low
Tx_Pause_Packets_Low
Tx_VLAN_Packets_Good_Low
Rx_Packet_Count_Good_Bad_Low
Rx_Octet_Count_Good_Bad_Low
Rx_Octet_Count_Good_Bad_High
Rx_Octet_Count_Good_Low
Rx_Octet_Count_Good_High
Rx_Broadcast_Packets_Good_Low
Rx_Multicast_Packets_Good_Low
Rx_CRC_Error_Packets_Low
Rx_Runt_Error_Packets
Rx_Jabber_Error_Packets
Rx_Undersize_Packets_Good
Rx_Oversize_Packets_Good
Rx_64Octets_Packets_Good_Bad_Low
Rx_65To127Octets_Packets_Good_Bad_Low
Rx_128To255Octets_Packets_Good_Bad_Low
Rx_256To511Octets_Packets_Good_Bad_Low
Rx_512To1023Octets_Packets_Good_Bad_Low
Rx_1024ToMaxOctets_Packets_Good_Bad_Low
Rx_Unicast_Packets_Good_Low
Rx_Length_Error_Packets_Low
Rx_OutofRange_Packets_Low
Rx_Pause_Packets_Low
Rx_FIFOOverflow_Packets_Low
Rx_VLAN_Packets_Good_Bad_Low
Rx_Watchdog_Error_Packets
Rx_Discard_Packets_Good_Bad_Low
Rx_Discard_Octets_Good_Bad_Low
Rx_Discard_Octets_Good_Bad_High
Rx_Alignment_Error_Packets
MMC_FPE_Tx_Interrupt
MMC_FPE_Tx_Interrupt_Mask
MMC_Tx_FPE_Fragment_Cntr
MMC_Tx_Hold_Req_Cntr
MMC_Tx_Gate_Orun_Cntr_Low
MMC_Tx_Gate_Orun_Cntr_High
MMC_FPE_Rx_Interrupt
MMC_FPE_Rx_Interrupt_Mask
MMC_Rx_Packet_Assembly_Err_Cntr
MMC_Rx_Packet_SMD_Err_Cntr
MMC_Rx_Packet_Assembly_OK_Cntr
MMC_Rx_FPE_Fragment_Cntr
Tx_Single_Collision_Good_Packets
Tx_Multiple_Collision_Good_Packets
Tx_Deferred_Packets
Tx_Late_Collision_Packets
Tx_Excessive_Collision_Packets
Tx_Carrier_Error_Packets
Tx_Excessive_Deferral_Error
MMC_IPC_Rx_Interrupt_Mask
MMC_IPC_Rx_Interrupt
RxIPv4_Good_Packets_Low
RxIPv4_Header_Error_Packets_Low
RxIPv4_No_Payload_Packets_Low
RxIPv4_Fragmented_Packets_Low
RxIPv4_UDP_Checksum_Disabled_Packets_Low
RxIPv6_Good_Packets_Low
RxIPv6_Header_Error_Packets_Low
RxIPv6_No_Payload_Packets_Low
RxUDP_Good_Packets_Low
RxUDP_Error_Packets_Low
RxTCP_Good_Packets_Low
RxTCP_Error_Packets_Low
RxICMP_Good_Packets_Low
RxICMP_Error_Packets_Low
RxIPv4_Good_Octets_Low
RxIPv4_Header_Error_Octets_Low
RxIPv4_No_Payload_Octets_Low
RxIPv4_Fragmented_Octets_Low
RxIPv4_UDP_Checksum_Disable_Octets_Low
RxIPv6_Good_Octets_Low
RxIPv6_Header_Error_Octets_Low
RxIPv6_No_Payload_Octets_Low
RxUDP_Good_Octets_Low
RxUDP_Error_Octets_Low
RxTCP_Good_Octets_Low
RxTCP_Error_Octets_Low
RxICMP_Good_Octets_Low
RxICMP_Error_Octets_Low
MAC_L3_L4_Address_Control
MAC_L3_L4_Data
MAC_ARP_Address
MAC_Timestamp_Control
MAC_Sub_Second_Increment
MAC_System_Time_Seconds
MAC_System_Time_Nanoseconds
MAC_System_Time_Seconds_Update
MAC_System_Time_Nanoseconds_Update
MAC_Timestamp_Addend
MAC_System_Time_Higher_Word_Seconds
MAC_Timestamp_Status
MAC_Tx_Timestamp_Status_Nanoseconds
MAC_Tx_Timestamp_Status_Seconds
MAC_Tx_Timestamp_Status_PktID
MAC_Auxiliary_Control
MAC_Auxiliary_Timestamp_Nanoseconds
MAC_Auxiliary_Timestamp_Seconds
MAC_Timestamp_Ingress_Asym_Corr
MAC_Timestamp_Egress_Asym_Corr
MAC_Timestamp_Ingress_Corr_Nanosecond
MAC_Timestamp_Ingress_Corr_Subnanosecond
MAC_Timestamp_Egress_Corr_Nanosecond
MAC_Timestamp_Egress_Corr_Subnanosecond
MAC_PPS_Control
MAC_PPS0_Target_Time_Seconds
MAC_PPS0_Target_Time_Nanoseconds
MAC_PPS0_Interval
MAC_PPS0_Width
MAC_PPS1_Target_Time_Seconds
MAC_PPS1_Target_Time_Nanoseconds
MAC_PPS1_Interval
MAC_PPS1_Width
MAC_PTO_Control
MAC_Source_Port_Identity0
MAC_Source_Port_Identity1
MAC_Source_Port_Identity2
MAC_Log_Message_Interval
2EMAC2_DWCXG_MTL Address Map
2EMAC2_DWCXG_MTL Summary
MTL_Operation_Mode
MTL_Debug_Control
MTL_Debug_Status
MTL_FIFO_Debug_Data
MTL_Interrupt_Status
MTL_RxQ_DMA_Map0
MTL_RxQ_DMA_Map1
MTL_TC_Prty_Map0
MTL_TC_Prty_Map1
MTL_TBS_CTRL
MTL_TBS_STATS
MTL_EST_Control
MTL_EST_Overhead
MTL_EST_Status
MTL_EST_Sch_Error
MTL_EST_Frm_Size_Error
MTL_EST_Frm_Size_Capture
MTL_EST_Intr_Enable
MTL_GCL_Control
MTL_GCL_Data
MTL_FPE_CTRL_STS
MTL_FPE_Advance
2EMAC2_DWCXG_MTL_TCQ0 Address Map
2EMAC2_DWCXG_MTL_TCQ0 Summary
MTL_TxQ0_Operation_Mode
MTL_TxQ0_Underflow
MTL_TxQ0_Debug
MTL_TC0_ETS_Control
MTL_TC0_ETS_Status
MTL_TC0_Quantum_Weight
MTL_RxQ0_Operation_Mode
MTL_RxQ0_Missed_Pkt_Overflow_Cnt
MTL_RxQ0_Debug
MTL_RxQ0_Control
MTL_RxQ0_Flow_Control
MTL_Q0_Interrupt_Enable
MTL_Q0_Interrupt_Status
2EMAC2_DWCXG_MTL_TCQ1 Address Map
2EMAC2_DWCXG_MTL_TCQ1 Summary
MTL_TxQ1_Operation_Mode
MTL_TxQ1_Underflow
MTL_TxQ1_Debug
MTL_TC1_ETS_Control
MTL_TC1_ETS_Status
MTL_TC1_Quantum_Weight
MTL_RxQ1_Operation_Mode
MTL_RxQ1_Missed_Pkt_Overflow_Cnt
MTL_RxQ1_Debug
MTL_RxQ1_Control
MTL_RxQ1_Flow_Control
MTL_Q1_Interrupt_Enable
MTL_Q1_Interrupt_Status
2EMAC2_DWCXG_MTL_TCQ2 Address Map
2EMAC2_DWCXG_MTL_TCQ2 Summary
MTL_TxQ2_Operation_Mode
MTL_TxQ2_Underflow
MTL_TxQ2_Debug
MTL_TC2_ETS_Control
MTL_TC2_ETS_Status
MTL_TC2_Quantum_Weight
MTL_RxQ2_Operation_Mode
MTL_RxQ2_Missed_Pkt_Overflow_Cnt
MTL_RxQ2_Debug
MTL_RxQ2_Control
MTL_RxQ2_Flow_Control
MTL_Q2_Interrupt_Enable
MTL_Q2_Interrupt_Status
2EMAC2_DWCXG_MTL_TCQ3 Address Map
2EMAC2_DWCXG_MTL_TCQ3 Summary
MTL_TxQ3_Operation_Mode
MTL_TxQ3_Underflow
MTL_TxQ3_Debug
MTL_TC3_ETS_Control
MTL_TC3_ETS_Status
MTL_TC3_Quantum_Weight
MTL_RxQ3_Operation_Mode
MTL_RxQ3_Missed_Pkt_Overflow_Cnt
MTL_RxQ3_Debug
MTL_RxQ3_Control
MTL_RxQ3_Flow_Control
MTL_Q3_Interrupt_Enable
MTL_Q3_Interrupt_Status
2EMAC2_DWCXG_MTL_TCQ4 Address Map
2EMAC2_DWCXG_MTL_TCQ4 Summary
MTL_TxQ4_Operation_Mode
MTL_TxQ4_Underflow
MTL_TxQ4_Debug
MTL_TC4_ETS_Control
MTL_TC4_ETS_Status
MTL_TC4_Quantum_Weight
MTL_RxQ4_Operation_Mode
MTL_RxQ4_Missed_Pkt_Overflow_Cnt
MTL_RxQ4_Debug
MTL_RxQ4_Control
MTL_RxQ4_Flow_Control
MTL_Q4_Interrupt_Enable
MTL_Q4_Interrupt_Status
2EMAC2_DWCXG_MTL_TCQ5 Address Map
2EMAC2_DWCXG_MTL_TCQ5 Summary
MTL_TxQ5_Operation_Mode
MTL_TxQ5_Underflow
MTL_TxQ5_Debug
MTL_TC5_ETS_Control
MTL_TC5_ETS_Status
MTL_TC5_Quantum_Weight
MTL_RxQ5_Operation_Mode
MTL_RxQ5_Missed_Pkt_Overflow_Cnt
MTL_RxQ5_Debug
MTL_RxQ5_Control
MTL_RxQ5_Flow_Control
MTL_Q5_Interrupt_Enable
MTL_Q5_Interrupt_Status
2EMAC2_DWCXG_MTL_TCQ6 Address Map
2EMAC2_DWCXG_MTL_TCQ6 Summary
MTL_TxQ6_Operation_Mode
MTL_TxQ6_Underflow
MTL_TxQ6_Debug
MTL_TC6_ETS_Control
MTL_TC6_ETS_Status
MTL_TC6_Quantum_Weight
MTL_RxQ6_Operation_Mode
MTL_RxQ6_Missed_Pkt_Overflow_Cnt
MTL_RxQ6_Debug
MTL_RxQ6_Control
MTL_RxQ6_Flow_Control
MTL_Q6_Interrupt_Enable
MTL_Q6_Interrupt_Status
2EMAC2_DWCXG_MTL_TCQ7 Address Map
2EMAC2_DWCXG_MTL_TCQ7 Summary
MTL_TxQ7_Operation_Mode
MTL_TxQ7_Underflow
MTL_TxQ7_Debug
MTL_TC7_ETS_Control
MTL_TC7_ETS_Status
MTL_TC7_Quantum_Weight
MTL_TC7_SendSlopeCredit
MTL_TC7_HiCredit
MTL_TC7_LoCredit
MTL_RxQ7_Operation_Mode
MTL_RxQ7_Missed_Pkt_Overflow_Cnt
MTL_RxQ7_Debug
MTL_RxQ7_Control
MTL_RxQ7_Flow_Control
MTL_Q7_Interrupt_Enable
MTL_Q7_Interrupt_Status
2EMAC2_DWCXG_DMA Address Map
2EMAC2_DWCXG_DMA Summary
DMA_Mode
DMA_SysBus_Mode
DMA_Interrupt_Status
AXI_Tx_AR_ACE_Control
AXI_Rx_AW_ACE_Control
AXI_TxRx_AWAR_ACE_Control
DMA_Debug_Status0
DMA_Debug_Status1
DMA_Debug_Status3
DMA_Tx_EDMA_Control
DMA_Rx_EDMA_Control
AXI_LPI_Entry_Interval
DMA_TBS_CTRL0
DMA_TBS_CTRL1
DMA_TBS_CTRL2
DMA_TBS_CTRL3
DMA_CH_Ind_Ctrl
DMA_CH_Ind_Data
2EMAC2_DWCXG_DMA_CH0 Address Map
2EMAC2_DWCXG_DMA_CH0 Summary
DMA_CH0_Control
DMA_CH0_Tx_Control
DMA_CH0_Rx_Control
DMA_CH0_Slot_Function_Control_Status
DMA_CH0_TxDesc_List_HAddress
DMA_CH0_TxDesc_List_LAddress
DMA_CH0_RxDesc_List_HAddress
DMA_CH0_RxDesc_List_LAddress
DMA_CH0_TxDesc_Tail_LPointer
DMA_CH0_RxDesc_Tail_LPointer
DMA_CH0_Tx_Control2
DMA_CH0_Rx_Control2
DMA_CH0_Interrupt_Enable
DMA_CH0_Rx_Interrupt_Watchdog_Timer
DMA_CH0_Current_App_TxDesc_L
DMA_CH0_Current_App_RxDesc_L
DMA_CH0_Current_App_TxBuffer_H
DMA_CH0_Current_App_TxBuffer_L
DMA_CH0_Current_App_RxBuffer_H
DMA_CH0_Current_App_RxBuffer_L
DMA_CH0_Status
DMA_CH0_Debug_Status
DMA_CH0_Desc_Mem_Cache_Fill_Level
DMA_CH0_Miss_Packet_Cnt
DMA_CH0_Tx_Data_Xfer_Ring_Offset
DMA_CH0_Rx_Data_Xfer_Ring_Offset
DMA_CH0_Tx_Desc_Write_Ring_Offset
DMA_CH0_Rx_Desc_Write_Ring_Offset
2EMAC2_DWCXG_DMA_CH1 Address Map
2EMAC2_DWCXG_DMA_CH1 Summary
DMA_CH1_Control
DMA_CH1_Tx_Control
DMA_CH1_Rx_Control
DMA_CH1_Slot_Function_Control_Status
DMA_CH1_TxDesc_List_HAddress
DMA_CH1_TxDesc_List_LAddress
DMA_CH1_RxDesc_List_HAddress
DMA_CH1_RxDesc_List_LAddress
DMA_CH1_TxDesc_Tail_LPointer
DMA_CH1_RxDesc_Tail_LPointer
DMA_CH1_Tx_Control2
DMA_CH1_Rx_Control2
DMA_CH1_Interrupt_Enable
DMA_CH1_Rx_Interrupt_Watchdog_Timer
DMA_CH1_Current_App_TxDesc_L
DMA_CH1_Current_App_RxDesc_L
DMA_CH1_Current_App_TxBuffer_H
DMA_CH1_Current_App_TxBuffer_L
DMA_CH1_Current_App_RxBuffer_H
DMA_CH1_Current_App_RxBuffer_L
DMA_CH1_Status
DMA_CH1_Debug_Status
DMA_CH1_Desc_Mem_Cache_Fill_Level
DMA_CH1_Miss_Packet_Cnt
DMA_CH1_Tx_Data_Xfer_Ring_Offset
DMA_CH1_Rx_Data_Xfer_Ring_Offset
DMA_CH1_Tx_Desc_Write_Ring_Offset
DMA_CH1_Rx_Desc_Write_Ring_Offset
2EMAC2_DWCXG_DMA_CH2 Address Map
2EMAC2_DWCXG_DMA_CH2 Summary
DMA_CH2_Control
DMA_CH2_Tx_Control
DMA_CH2_Rx_Control
DMA_CH2_Slot_Function_Control_Status
DMA_CH2_TxDesc_List_HAddress
DMA_CH2_TxDesc_List_LAddress
DMA_CH2_RxDesc_List_HAddress
DMA_CH2_RxDesc_List_LAddress
DMA_CH2_TxDesc_Tail_LPointer
DMA_CH2_RxDesc_Tail_LPointer
DMA_CH2_Tx_Control2
DMA_CH2_Rx_Control2
DMA_CH2_Interrupt_Enable
DMA_CH2_Rx_Interrupt_Watchdog_Timer
DMA_CH2_Current_App_TxDesc_L
DMA_CH2_Current_App_RxDesc_L
DMA_CH2_Current_App_TxBuffer_H
DMA_CH2_Current_App_TxBuffer_L
DMA_CH2_Current_App_RxBuffer_H
DMA_CH2_Current_App_RxBuffer_L
DMA_CH2_Status
DMA_CH2_Debug_Status
DMA_CH2_Desc_Mem_Cache_Fill_Level
DMA_CH2_Miss_Packet_Cnt
DMA_CH2_Tx_Data_Xfer_Ring_Offset
DMA_CH2_Rx_Data_Xfer_Ring_Offset
DMA_CH2_Tx_Desc_Write_Ring_Offset
DMA_CH2_Rx_Desc_Write_Ring_Offset
2EMAC2_DWCXG_DMA_CH3 Address Map
2EMAC2_DWCXG_DMA_CH3 Summary
DMA_CH3_Control
DMA_CH3_Tx_Control
DMA_CH3_Rx_Control
DMA_CH3_Slot_Function_Control_Status
DMA_CH3_TxDesc_List_HAddress
DMA_CH3_TxDesc_List_LAddress
DMA_CH3_RxDesc_List_HAddress
DMA_CH3_RxDesc_List_LAddress
DMA_CH3_TxDesc_Tail_LPointer
DMA_CH3_RxDesc_Tail_LPointer
DMA_CH3_Tx_Control2
DMA_CH3_Rx_Control2
DMA_CH3_Interrupt_Enable
DMA_CH3_Rx_Interrupt_Watchdog_Timer
DMA_CH3_Current_App_TxDesc_L
DMA_CH3_Current_App_RxDesc_L
DMA_CH3_Current_App_TxBuffer_H
DMA_CH3_Current_App_TxBuffer_L
DMA_CH3_Current_App_RxBuffer_H
DMA_CH3_Current_App_RxBuffer_L
DMA_CH3_Status
DMA_CH3_Debug_Status
DMA_CH3_Desc_Mem_Cache_Fill_Level
DMA_CH3_Miss_Packet_Cnt
DMA_CH3_Tx_Data_Xfer_Ring_Offset
DMA_CH3_Rx_Data_Xfer_Ring_Offset
DMA_CH3_Tx_Desc_Write_Ring_Offset
DMA_CH3_Rx_Desc_Write_Ring_Offset
2EMAC2_DWCXG_DMA_CH4 Address Map
2EMAC2_DWCXG_DMA_CH4 Summary
DMA_CH4_Control
DMA_CH4_Tx_Control
DMA_CH4_Rx_Control
DMA_CH4_Slot_Function_Control_Status
DMA_CH4_TxDesc_List_HAddress
DMA_CH4_TxDesc_List_LAddress
DMA_CH4_RxDesc_List_HAddress
DMA_CH4_RxDesc_List_LAddress
DMA_CH4_TxDesc_Tail_LPointer
DMA_CH4_RxDesc_Tail_LPointer
DMA_CH4_Tx_Control2
DMA_CH4_Rx_Control2
DMA_CH4_Interrupt_Enable
DMA_CH4_Rx_Interrupt_Watchdog_Timer
DMA_CH4_Current_App_TxDesc_L
DMA_CH4_Current_App_RxDesc_L
DMA_CH4_Current_App_TxBuffer_H
DMA_CH4_Current_App_TxBuffer_L
DMA_CH4_Current_App_RxBuffer_H
DMA_CH4_Current_App_RxBuffer_L
DMA_CH4_Status
DMA_CH4_Debug_Status
DMA_CH4_Desc_Mem_Cache_Fill_Level
DMA_CH4_Miss_Packet_Cnt
DMA_CH4_Tx_Data_Xfer_Ring_Offset
DMA_CH4_Rx_Data_Xfer_Ring_Offset
DMA_CH4_Tx_Desc_Write_Ring_Offset
DMA_CH4_Rx_Desc_Write_Ring_Offset
2EMAC2_DWCXG_DMA_CH5 Address Map
2EMAC2_DWCXG_DMA_CH5 Summary
DMA_CH5_Control
DMA_CH5_Tx_Control
DMA_CH5_Rx_Control
DMA_CH5_Slot_Function_Control_Status
DMA_CH5_TxDesc_List_HAddress
DMA_CH5_TxDesc_List_LAddress
DMA_CH5_RxDesc_List_HAddress
DMA_CH5_RxDesc_List_LAddress
DMA_CH5_TxDesc_Tail_LPointer
DMA_CH5_RxDesc_Tail_LPointer
DMA_CH5_Tx_Control2
DMA_CH5_Rx_Control2
DMA_CH5_Interrupt_Enable
DMA_CH5_Rx_Interrupt_Watchdog_Timer
DMA_CH5_Current_App_TxDesc_L
DMA_CH5_Current_App_RxDesc_L
DMA_CH5_Current_App_TxBuffer_H
DMA_CH5_Current_App_TxBuffer_L
DMA_CH5_Current_App_RxBuffer_H
DMA_CH5_Current_App_RxBuffer_L
DMA_CH5_Status
DMA_CH5_Debug_Status
DMA_CH5_Desc_Mem_Cache_Fill_Level
DMA_CH5_Miss_Packet_Cnt
DMA_CH5_Tx_Data_Xfer_Ring_Offset
DMA_CH5_Rx_Data_Xfer_Ring_Offset
DMA_CH5_Tx_Desc_Write_Ring_Offset
DMA_CH5_Rx_Desc_Write_Ring_Offset
2EMAC2_DWCXG_DMA_CH6 Address Map
2EMAC2_DWCXG_DMA_CH6 Summary
DMA_CH6_Control
DMA_CH6_Tx_Control
DMA_CH6_Rx_Control
DMA_CH6_Slot_Function_Control_Status
DMA_CH6_TxDesc_List_HAddress
DMA_CH6_TxDesc_List_LAddress
DMA_CH6_RxDesc_List_HAddress
DMA_CH6_RxDesc_List_LAddress
DMA_CH6_TxDesc_Tail_LPointer
DMA_CH6_RxDesc_Tail_LPointer
DMA_CH6_Tx_Control2
DMA_CH6_Rx_Control2
DMA_CH6_Interrupt_Enable
DMA_CH6_Rx_Interrupt_Watchdog_Timer
DMA_CH6_Current_App_TxDesc_L
DMA_CH6_Current_App_RxDesc_L
DMA_CH6_Current_App_TxBuffer_H
DMA_CH6_Current_App_TxBuffer_L
DMA_CH6_Current_App_RxBuffer_H
DMA_CH6_Current_App_RxBuffer_L
DMA_CH6_Status
DMA_CH6_Debug_Status
DMA_CH6_Desc_Mem_Cache_Fill_Level
DMA_CH6_Miss_Packet_Cnt
DMA_CH6_Tx_Data_Xfer_Ring_Offset
DMA_CH6_Rx_Data_Xfer_Ring_Offset
DMA_CH6_Tx_Desc_Write_Ring_Offset
DMA_CH6_Rx_Desc_Write_Ring_Offset
2EMAC2_DWCXG_DMA_CH7 Address Map
2EMAC2_DWCXG_DMA_CH7 Summary
DMA_CH7_Control
DMA_CH7_Tx_Control
DMA_CH7_Rx_Control
DMA_CH7_Slot_Function_Control_Status
DMA_CH7_TxDesc_List_HAddress
DMA_CH7_TxDesc_List_LAddress
DMA_CH7_RxDesc_List_HAddress
DMA_CH7_RxDesc_List_LAddress
DMA_CH7_TxDesc_Tail_LPointer
DMA_CH7_RxDesc_Tail_LPointer
DMA_CH7_Tx_Control2
DMA_CH7_Rx_Control2
DMA_CH7_Interrupt_Enable
DMA_CH7_Rx_Interrupt_Watchdog_Timer
DMA_CH7_Current_App_TxDesc_L
DMA_CH7_Current_App_RxDesc_L
DMA_CH7_Current_App_TxBuffer_H
DMA_CH7_Current_App_TxBuffer_L
DMA_CH7_Current_App_RxBuffer_H
DMA_CH7_Current_App_RxBuffer_L
DMA_CH7_Status
DMA_CH7_Debug_Status
DMA_CH7_Desc_Mem_Cache_Fill_Level
DMA_CH7_Miss_Packet_Cnt
DMA_CH7_Tx_Data_Xfer_Ring_Offset
DMA_CH7_Rx_Data_Xfer_Ring_Offset
DMA_CH7_Tx_Desc_Write_Ring_Offset
DMA_CH7_Rx_Desc_Write_Ring_Offset
ECC Address Block Group
usbotg0_ecc Address Map
usbotg0_ecc Summary
IP_REV_ID
IP_REV_ID2
CTRL
INITSTAT
ERRINTEN
ERRINTENS
ERRINTENR
INTMODE
INTSTAT
INTTEST
MODSTAT
DERRADDRA
SERRADDRA
DERRADDRB
SERRADDRB
SERRCNTREG
ECC_Addrbus
ECC_RData0bus
ECC_RData1bus
ECC_RData2bus
ECC_RData3bus
ECC_WData0bus
ECC_WData1bus
ECC_WData2bus
ECC_WData3bus
ECC_RDataecc0bus
ECC_RDataecc1bus
ECC_WDataecc0bus
ECC_WDataecc1bus
ECC_dbytectrl
ECC_accctrl
ECC_startacc
ECC_wdctrl
ECC_DECODERSTAT
SERRLKUPA0
SERRLKUPB0
usb1_tx_ecc Address Map
usb1_tx_ecc Summary
IP_REV_ID
IP_REV_ID2
CTRL
INITSTAT
ERRINTEN
ERRINTENS
ERRINTENR
INTMODE
INTSTAT
INTTEST
MODSTAT
DERRADDRA
SERRADDRA
DERRADDRB
SERRADDRB
SERRCNTREG
ECC_Addrbus
ECC_RData0bus
ECC_RData1bus
ECC_RData2bus
ECC_RData3bus
ECC_WData0bus
ECC_WData1bus
ECC_WData2bus
ECC_WData3bus
ECC_RDataecc0bus
ECC_RDataecc1bus
ECC_WDataecc0bus
ECC_WDataecc1bus
ECC_dbytectrl
ECC_accctrl
ECC_startacc
ECC_wdctrl
ECC_DECODERSTAT
SERRLKUPA0
SERRLKUPB0
usb1_rx_ecc Address Map
usb1_rx_ecc Summary
IP_REV_ID
IP_REV_ID2
CTRL
INITSTAT
ERRINTEN
ERRINTENS
ERRINTENR
INTMODE
INTSTAT
INTTEST
MODSTAT
DERRADDRA
SERRADDRA
DERRADDRB
SERRADDRB
SERRCNTREG
ECC_Addrbus
ECC_RData0bus
ECC_RData1bus
ECC_RData2bus
ECC_RData3bus
ECC_WData0bus
ECC_WData1bus
ECC_WData2bus
ECC_WData3bus
ECC_RDataecc0bus
ECC_RDataecc1bus
ECC_WDataecc0bus
ECC_WDataecc1bus
ECC_dbytectrl
ECC_accctrl
ECC_startacc
ECC_wdctrl
ECC_DECODERSTAT
SERRLKUPA0
SERRLKUPB0
usb1_cache_ecc Address Map
usb1_cache_ecc Summary
IP_REV_ID
IP_REV_ID2
CTRL
INITSTAT
ERRINTEN
ERRINTENS
ERRINTENR
INTMODE
INTSTAT
INTTEST
MODSTAT
DERRADDRA
SERRADDRA
DERRADDRB
SERRADDRB
SERRCNTREG
ECC_Addrbus
ECC_RData0bus
ECC_RData1bus
ECC_RData2bus
ECC_RData3bus
ECC_WData0bus
ECC_WData1bus
ECC_WData2bus
ECC_WData3bus
ECC_RDataecc0bus
ECC_RDataecc1bus
ECC_WDataecc0bus
ECC_WDataecc1bus
ECC_dbytectrl
ECC_accctrl
ECC_startacc
ECC_wdctrl
ECC_DECODERSTAT
SERRLKUPA0
SERRLKUPB0
emac2_tx_ecc Address Map
emac2_tx_ecc Summary
IP_REV_ID
IP_REV_ID2
CTRL
INITSTAT
ERRINTEN
ERRINTENS
ERRINTENR
INTMODE
INTSTAT
INTTEST
MODSTAT
DERRADDRA
SERRADDRA
DERRADDRB
SERRADDRB
SERRCNTREG
ECC_Addrbus
ECC_RData0bus
ECC_RData1bus
ECC_RData2bus
ECC_RData3bus
ECC_WData0bus
ECC_WData1bus
ECC_WData2bus
ECC_WData3bus
ECC_RDataecc0bus
ECC_RDataecc1bus
ECC_WDataecc0bus
ECC_WDataecc1bus
ECC_dbytectrl
ECC_accctrl
ECC_startacc
ECC_wdctrl
ECC_DECODERSTAT
SERRLKUPA0
SERRLKUPB0
emac2_rx_ecc Address Map
emac2_rx_ecc Summary
IP_REV_ID
IP_REV_ID2
CTRL
INITSTAT
ERRINTEN
ERRINTENS
ERRINTENR
INTMODE
INTSTAT
INTTEST
MODSTAT
DERRADDRA
SERRADDRA
DERRADDRB
SERRADDRB
SERRCNTREG
ECC_Addrbus
ECC_RData0bus
ECC_RData1bus
ECC_RData2bus
ECC_RData3bus
ECC_WData0bus
ECC_WData1bus
ECC_WData2bus
ECC_WData3bus
ECC_RDataecc0bus
ECC_RDataecc1bus
ECC_WDataecc0bus
ECC_WDataecc1bus
ECC_dbytectrl
ECC_accctrl
ECC_startacc
ECC_wdctrl
ECC_DECODERSTAT
SERRLKUPA0
SERRLKUPB0
emac1_tx_ecc Address Map
emac1_tx_ecc Summary
IP_REV_ID
IP_REV_ID2
CTRL
INITSTAT
ERRINTEN
ERRINTENS
ERRINTENR
INTMODE
INTSTAT
INTTEST
MODSTAT
DERRADDRA
SERRADDRA
DERRADDRB
SERRADDRB
SERRCNTREG
ECC_Addrbus
ECC_RData0bus
ECC_RData1bus
ECC_RData2bus
ECC_RData3bus
ECC_WData0bus
ECC_WData1bus
ECC_WData2bus
ECC_WData3bus
ECC_RDataecc0bus
ECC_RDataecc1bus
ECC_WDataecc0bus
ECC_WDataecc1bus
ECC_dbytectrl
ECC_accctrl
ECC_startacc
ECC_wdctrl
ECC_DECODERSTAT
SERRLKUPA0
SERRLKUPB0
emac1_rx_ecc Address Map
emac1_rx_ecc Summary
IP_REV_ID
IP_REV_ID2
CTRL
INITSTAT
ERRINTEN
ERRINTENS
ERRINTENR
INTMODE
INTSTAT
INTTEST
MODSTAT
DERRADDRA
SERRADDRA
DERRADDRB
SERRADDRB
SERRCNTREG
ECC_Addrbus
ECC_RData0bus
ECC_RData1bus
ECC_RData2bus
ECC_RData3bus
ECC_WData0bus
ECC_WData1bus
ECC_WData2bus
ECC_WData3bus
ECC_RDataecc0bus
ECC_RDataecc1bus
ECC_WDataecc0bus
ECC_WDataecc1bus
ECC_dbytectrl
ECC_accctrl
ECC_startacc
ECC_wdctrl
ECC_DECODERSTAT
SERRLKUPA0
SERRLKUPB0
emac0_tx_ecc Address Map
emac0_tx_ecc Summary
IP_REV_ID
IP_REV_ID2
CTRL
INITSTAT
ERRINTEN
ERRINTENS
ERRINTENR
INTMODE
INTSTAT
INTTEST
MODSTAT
DERRADDRA
SERRADDRA
DERRADDRB
SERRADDRB
SERRCNTREG
ECC_Addrbus
ECC_RData0bus
ECC_RData1bus
ECC_RData2bus
ECC_RData3bus
ECC_WData0bus
ECC_WData1bus
ECC_WData2bus
ECC_WData3bus
ECC_RDataecc0bus
ECC_RDataecc1bus
ECC_WDataecc0bus
ECC_WDataecc1bus
ECC_dbytectrl
ECC_accctrl
ECC_startacc
ECC_wdctrl
ECC_DECODERSTAT
SERRLKUPA0
SERRLKUPB0
emac0_rx_ecc Address Map
emac0_rx_ecc Summary
IP_REV_ID
IP_REV_ID2
CTRL
INITSTAT
ERRINTEN
ERRINTENS
ERRINTENR
INTMODE
INTSTAT
INTTEST
MODSTAT
DERRADDRA
SERRADDRA
DERRADDRB
SERRADDRB
SERRCNTREG
ECC_Addrbus
ECC_RData0bus
ECC_RData1bus
ECC_RData2bus
ECC_RData3bus
ECC_WData0bus
ECC_WData1bus
ECC_WData2bus
ECC_WData3bus
ECC_RDataecc0bus
ECC_RDataecc1bus
ECC_WDataecc0bus
ECC_WDataecc1bus
ECC_dbytectrl
ECC_accctrl
ECC_startacc
ECC_wdctrl
ECC_DECODERSTAT
SERRLKUPA0
SERRLKUPB0
OCRAM_registers Address Block Group
OCRAM_firewall Address Map
OCRAM_firewall Summary
enable
enable_set
enable_clear
region0_base_adresss
region0_limit_adresss
region0_access
region1_base_adresss
region1_limit_adresss
region1_access
region2_base_adresss
region2_limit_adresss
region2_access
region3_base_adresss
region3_limit_adresss
region3_access
OCRAM_ecc Address Map
OCRAM_ecc Summary
IP_REV_ID
IP_REV_ID2
CTRL
INITSTAT
ERRINTEN
ERRINTENS
ERRINTENR
INTMODE
INTSTAT
INTTEST
MODSTAT
DERRADDRA
SERRADDRA
DERRADDRB
SERRADDRB
SERRCNTREG
ECC_Addrbus
ECC_RData0bus
ECC_RData1bus
ECC_RData2bus
ECC_RData3bus
ECC_WData0bus
ECC_WData1bus
ECC_WData2bus
ECC_WData3bus
ECC_RDataecc0bus
ECC_RDataecc1bus
ECC_WDataecc0bus
ECC_WDataecc1bus
ECC_dbytectrl
ECC_accctrl
ECC_startacc
ECC_wdctrl
ECC_DECODERSTAT
SERRLKUPA0
SERRLKUPB0
PSI Address Block Group
PSI-UART Address Map
PSI-UART Summary
RBR
IER
IIR
LCR
MCR
LSR
MSR
SCR
SRBR0
SRBR1
SRBR2
SRBR3
SRBR4
SRBR5
SRBR6
SRBR7
SRBR8
SRBR9
SRBR10
SRBR11
SRBR12
SRBR13
SRBR14
SRBR15
FAR
TFR
RFW
USR
TFL
RFL
SRR
SRTS
SBCR
SDMAM
SFE
SRT
STET
HTX
DMASA
CPR
UCV
CTR
SDMMC_SEG Address Map
SDMMC_SEG Summary
CTRL
PWREN
CLKDIV
CLKSRC
CLKENA
TMOUT
CTYPE
BLKSIZ
BYTCNT
INTMASK
CMDARG
CMD
RESP0
RESP1
RESP2
RESP3
MINTSTS
RINTSTS
STATUS
FIFOTH
CDETECT
WRTPRT
GPIO
TCBCNT
TBBCNT
DEBNCE
USRID
VERID
HCON
UHS_REG
RST_n
BMOD
PLDMND
DBADDR
IDSTS
IDINTEN
DSCADDR
BUFADDR
CARDTHRCTL
BACK_END_POWER_R
UHS_REG_EXT
EMMC_DDR_REG
ENABLE_SHIFT
DATA
QSPI_csr Address Map
QSPI_csr Summary
cfg
devrd
devwr
delay
rddatacap
devsz
srampart
indaddrtrig
dmaper
remapaddr
modebit
sramfill
txthresh
rxthresh
irqstat
irqmask
lowwrprot
uppwrprot
wrprot
indrd
indrdwater
indrdstaddr
indrdcnt
indwr
indwrwater
indwrstaddr
indwrcnt
flashcmd
flashcmdaddr
flashcmdrddatalo
flashcmdrddataup
flashcmdwrdatalo
flashcmdwrdataup
moduleid
QSPI_data Address Map
PSI_mailbox Address Map
PSI_mailbox Address Map
PSI_mailbox Address Map
PSI_mailbox Address Map
i2c_1 Address Map
i2c_1 Summary
IC_CON
IC_TAR
IC_SAR
IC_DATA_CMD
IC_SS_SCL_HCNT
IC_SS_SCL_LCNT
IC_FS_SCL_HCNT
IC_FS_SCL_LCNT
IC_INTR_STAT
IC_INTR_MASK
IC_RAW_INTR_STAT
IC_RX_TL
IC_TX_TL
IC_CLR_INTR
IC_CLR_RX_UNDER
IC_CLR_RX_OVER
IC_CLR_TX_OVER
IC_CLR_RD_REQ
IC_CLR_TX_ABRT
IC_CLR_RX_DONE
IC_CLR_ACTIVITY
IC_CLR_STOP_DET
IC_CLR_START_DET
IC_CLR_GEN_CALL
IC_ENABLE
IC_STATUS
IC_TXFLR
IC_RXFLR
IC_SDA_HOLD
IC_TX_ABRT_SOURCE
IC_SLV_DATA_NACK_ONLY
IC_DMA_CR
IC_DMA_TDLR
IC_DMA_RDLR
IC_SDA_SETUP
IC_ACK_GENERAL_CALL
IC_ENABLE_STATUS
IC_FS_SPKLEN
IC_CLR_RESTART_DET
IC_SCL_STUCK_AT_LOW_TIMEOUT
IC_SDA_STUCK_AT_LOW_TIMEOUT
IC_CLR_SCL_STUCK_DET
IC_SMBUS_CLK_LOW_SEXT
IC_SMBUS_CLK_LOW_MEXT
IC_SMBUS_THIGH_MAX_IDLE_COUNT
IC_SMBUS_INTR_STAT
IC_SMBUS_INTR_MASK
IC_SMBUS_RAW_INTR_STAT
IC_CLR_SMBUS_INTR
IC_COMP_PARAM_1
IC_COMP_VERSION
IC_COMP_TYPE
i2c_0 Address Map
i2c_0 Summary
IC_CON
IC_TAR
IC_SAR
IC_DATA_CMD
IC_SS_SCL_HCNT
IC_SS_SCL_LCNT
IC_FS_SCL_HCNT
IC_FS_SCL_LCNT
IC_INTR_STAT
IC_INTR_MASK
IC_RAW_INTR_STAT
IC_RX_TL
IC_TX_TL
IC_CLR_INTR
IC_CLR_RX_UNDER
IC_CLR_RX_OVER
IC_CLR_TX_OVER
IC_CLR_RD_REQ
IC_CLR_TX_ABRT
IC_CLR_RX_DONE
IC_CLR_ACTIVITY
IC_CLR_STOP_DET
IC_CLR_START_DET
IC_CLR_GEN_CALL
IC_ENABLE
IC_STATUS
IC_TXFLR
IC_RXFLR
IC_SDA_HOLD
IC_TX_ABRT_SOURCE
IC_SLV_DATA_NACK_ONLY
IC_DMA_CR
IC_DMA_TDLR
IC_DMA_RDLR
IC_SDA_SETUP
IC_ACK_GENERAL_CALL
IC_ENABLE_STATUS
IC_FS_SPKLEN
IC_CLR_RESTART_DET
IC_COMP_PARAM_1
IC_COMP_VERSION
IC_COMP_TYPE
SDMMC_ecc Address Map
SDMMC_ecc Summary
IP_REV_ID
IP_REV_ID2
CTRL
INITSTAT
ERRINTEN
ERRINTENS
ERRINTENR
INTMODE
INTSTAT
INTTEST
MODSTAT
DERRADDRA
SERRADDRA
DERRADDRB
SERRADDRB
SERRCNTREG
ECC_Addrbus
ECC_RData0bus
ECC_RData1bus
ECC_RData2bus
ECC_RData3bus
ECC_WData0bus
ECC_WData1bus
ECC_WData2bus
ECC_WData3bus
ECC_RDataecc0bus
ECC_RDataecc1bus
ECC_WDataecc0bus
ECC_WDataecc1bus
ECC_dbytectrl
ECC_accctrl
ECC_startacc
ECC_wdctrl
ECC_DECODERSTAT
SERRLKUPA0
SERRLKUPB0
QSPI_ecc Address Map
QSPI_ecc Summary
IP_REV_ID
IP_REV_ID2
CTRL
INITSTAT
ERRINTEN
ERRINTENS
ERRINTENR
INTMODE
INTSTAT
INTTEST
MODSTAT
DERRADDRA
SERRADDRA
DERRADDRB
SERRADDRB
SERRCNTREG
ECC_Addrbus
ECC_RData0bus
ECC_RData1bus
ECC_RData2bus
ECC_RData3bus
ECC_WData0bus
ECC_WData1bus
ECC_WData2bus
ECC_WData3bus
ECC_RDataecc0bus
ECC_RDataecc1bus
ECC_WDataecc0bus
ECC_WDataecc1bus
ECC_dbytectrl
ECC_accctrl
ECC_startacc
ECC_wdctrl
ECC_DECODERSTAT
SERRLKUPA0
SERRLKUPB0
USBOTG Address Block Group
intreg Address Map
intreg Summary
GOTGCTL
GOTGINT
GAHBCFG
GUSBCFG
GRSTCTL
GINTSTS
GINTMSK
GRXSTSR
GRXSTSP
GRXFSIZ
GNPTXFSIZ
GNPTXSTS
GPVNDCTL
GGPIO
GUID
GSNPSID
GHWCFG1
GHWCFG2
GHWCFG3
GHWCFG4
GDFIFOCFG
HPTXFSIZ
DIEPTXF1
DIEPTXF2
DIEPTXF3
DIEPTXF4
DIEPTXF5
DIEPTXF6
DIEPTXF7
DIEPTXF8
DIEPTXF9
DIEPTXF10
DIEPTXF11
DIEPTXF12
DIEPTXF13
DIEPTXF14
DIEPTXF15
HCFG
HFIR
HFNUM
HPTXSTS
HAINT
HAINTMSK
HFLBAddr
HPRT
HCCHAR0
HCSPLT0
HCINT0
HCINTMSK0
HCTSIZ0
HCDMA0
HCDMAB0
HCCHAR1
HCSPLT1
HCINT1
HCINTMSK1
HCTSIZ1
HCDMA1
HCDMAB1
HCCHAR2
HCSPLT2
HCINT2
HCINTMSK2
HCTSIZ2
HCDMA2
HCDMAB2
HCCHAR3
HCSPLT3
HCINT3
HCINTMSK3
HCTSIZ3
HCDMA3
HCDMAB3
HCCHAR4
HCSPLT4
HCINT4
HCINTMSK4
HCTSIZ4
HCDMA4
HCDMAB4
HCCHAR5
HCSPLT5
HCINT5
HCINTMSK5
HCTSIZ5
HCDMA5
HCDMAB5
HCCHAR6
HCSPLT6
HCINT6
HCINTMSK6
HCTSIZ6
HCDMA6
HCDMAB6
HCCHAR7
HCSPLT7
HCINT7
HCINTMSK7
HCTSIZ7
HCDMA7
HCDMAB7
HCCHAR8
HCSPLT8
HCINT8
HCINTMSK8
HCTSIZ8
HCDMA8
HCDMAB8
HCCHAR9
HCSPLT9
HCINT9
HCINTMSK9
HCTSIZ9
HCDMA9
HCDMAB9
HCCHAR10
HCSPLT10
HCINT10
HCINTMSK10
HCTSIZ10
HCDMA10
HCDMAB10
HCCHAR11
HCSPLT11
HCINT11
HCINTMSK11
HCTSIZ11
HCDMA11
HCDMAB11
HCCHAR12
HCSPLT12
HCINT12
HCINTMSK12
HCTSIZ12
HCDMA12
HCDMAB12
HCCHAR13
HCSPLT13
HCINT13
HCINTMSK13
HCTSIZ13
HCDMA13
HCDMAB13
HCCHAR14
HCSPLT14
HCINT14
HCINTMSK14
HCTSIZ14
HCDMA14
HCDMAB14
HCCHAR15
HCSPLT15
HCINT15
HCINTMSK15
HCTSIZ15
HCDMA15
HCDMAB15
DCFG
DCTL
DSTS
DIEPMSK
DOEPMSK
DAINT
DAINTMSK
DVBUSDIS
DVBUSPULSE
DTHRCTL
DIEPEMPMSK
DIEPCTL0
DIEPINT0
DIEPTSIZ0
DIEPDMA0
DTXFSTS0
DIEPDMAB0
DIEPCTL1
DIEPINT1
DIEPTSIZ1
DIEPDMA1
DTXFSTS1
DIEPDMAB1
DIEPCTL2
DIEPINT2
DIEPTSIZ2
DIEPDMA2
DTXFSTS2
DIEPDMAB2
DIEPCTL3
DIEPINT3
DIEPTSIZ3
DIEPDMA3
DTXFSTS3
DIEPDMAB3
DIEPCTL4
DIEPINT4
DIEPTSIZ4
DIEPDMA4
DTXFSTS4
DIEPDMAB4
DIEPCTL5
DIEPINT5
DIEPTSIZ5
DIEPDMA5
DTXFSTS5
DIEPDMAB5
DIEPCTL6
DIEPINT6
DIEPTSIZ6
DIEPDMA6
DTXFSTS6
DIEPDMAB6
DIEPCTL7
DIEPINT7
DIEPTSIZ7
DIEPDMA7
DTXFSTS7
DIEPDMAB7
DIEPCTL8
DIEPINT8
DIEPTSIZ8
DIEPDMA8
DTXFSTS8
DIEPDMAB8
DIEPCTL9
DIEPINT9
DIEPTSIZ9
DIEPDMA9
DTXFSTS9
DIEPDMAB9
DIEPCTL10
DIEPINT10
DIEPTSIZ10
DIEPDMA10
DTXFSTS10
DIEPDMAB10
DIEPCTL11
DIEPINT11
DIEPTSIZ11
DIEPDMA11
DTXFSTS11
DIEPDMAB11
DIEPCTL12
DIEPINT12
DIEPTSIZ12
DIEPDMA12
DTXFSTS12
DIEPDMAB12
DIEPCTL13
DIEPINT13
DIEPTSIZ13
DIEPDMA13
DTXFSTS13
DIEPDMAB13
DIEPCTL14
DIEPINT14
DIEPTSIZ14
DIEPDMA14
DTXFSTS14
DIEPDMAB14
DIEPCTL15
DIEPINT15
DIEPTSIZ15
DIEPDMA15
DTXFSTS15
DIEPDMAB15
DOEPCTL0
DOEPINT0
DOEPTSIZ0
DOEPDMA0
DOEPDMAB0
DOEPCTL1
DOEPINT1
DOEPTSIZ1
DOEPDMA1
DOEPDMAB1
DOEPCTL2
DOEPINT2
DOEPTSIZ2
DOEPDMA2
DOEPDMAB2
DOEPCTL3
DOEPINT3
DOEPTSIZ3
DOEPDMA3
DOEPDMAB3
DOEPCTL4
DOEPINT4
DOEPTSIZ4
DOEPDMA4
DOEPDMAB4
DOEPCTL5
DOEPINT5
DOEPTSIZ5
DOEPDMA5
DOEPDMAB5
DOEPCTL6
DOEPINT6
DOEPTSIZ6
DOEPDMA6
DOEPDMAB6
DOEPCTL7
DOEPINT7
DOEPTSIZ7
DOEPDMA7
DOEPDMAB7
DOEPCTL8
DOEPINT8
DOEPTSIZ8
DOEPDMA8
DOEPDMAB8
DOEPCTL9
DOEPINT9
DOEPTSIZ9
DOEPDMA9
DOEPDMAB9
DOEPCTL10
DOEPINT10
DOEPTSIZ10
DOEPDMA10
DOEPDMAB10
DOEPCTL11
DOEPINT11
DOEPTSIZ11
DOEPDMA11
DOEPDMAB11
DOEPCTL12
DOEPINT12
DOEPTSIZ12
DOEPDMA12
DOEPDMAB12
DOEPCTL13
DOEPINT13
DOEPTSIZ13
DOEPDMA13
DOEPDMAB13
DOEPCTL14
DOEPINT14
DOEPTSIZ14
DOEPDMA14
DOEPDMAB14
DOEPCTL15
DOEPINT15
DOEPTSIZ15
DOEPDMA15
DOEPDMAB15
PCGCCTL
DWC_otg_DFIFO_0 Address Map
DWC_otg_DFIFO_1 Address Map
DWC_otg_DFIFO_2 Address Map
DWC_otg_DFIFO_3 Address Map
DWC_otg_DFIFO_4 Address Map
DWC_otg_DFIFO_5 Address Map
DWC_otg_DFIFO_6 Address Map
DWC_otg_DFIFO_7 Address Map
DWC_otg_DFIFO_8 Address Map
DWC_otg_DFIFO_9 Address Map
DWC_otg_DFIFO_10 Address Map
DWC_otg_DFIFO_11 Address Map
DWC_otg_DFIFO_12 Address Map
DWC_otg_DFIFO_13 Address Map
DWC_otg_DFIFO_14 Address Map
DWC_otg_DFIFO_15 Address Map
DWC_otg_DFIFO_Direct_access Address Map
NAND Address Block Group
rf_cmd_stat_regs Address Map
rf_cmd_stat_regs Summary
cmd_reg0
cmd_reg1
cmd_reg2
cmd_reg3
cmd_status_ptr
cmd_status
cmd_status_ext
cmd_reg4
cmd_reg5
cmd_reg6
intr_status
intr_enable
ctrl_status
trd_status
trd_error_intr_status
trd_error_intr_en
trd_comp_intr_status
dma_target_error_l
dma_target_error_h
boot_status
trd_timeout_intr_status
trd_timeout_intr_en
rf_ctrl_config Address Map
rf_ctrl_config Summary
transfer_cfg_0
transfer_cfg_1
long_polling
short_polling
rdst_ctrl_0
rdst_ctrl_1
lun_status_cmd
lun_interleaved_cmd
lun_addr_offset
nf_dev_layout
ecc_config_0
ecc_config_1
device_ctrl
multiplane_config
cache_config
dma_settings
sdma_size
sdma_trd_num
time_out
sdma_addr0
sdma_addr1
fifo_trigg_level
remap_ctrl
remap_mask
remap_access
remap_log_addr
remap_phys_addr
control_data_ctrl
rf_di_regs Address Map
rf_di_regs Summary
di_control
di_inject0
di_inject1
di_error_reg_addr
di_inject2
rf_controller_params Address Map
rf_controller_params Summary
ctrl_version
ctrl_features_reg
manufacturer_id
nf_device_areas
device_params_0
device_params_1
device_features
device_blocks_per_lun
device_revision
onfi_timing_modes_0
onfi_timing_modes_1
onfi_iterlv_op_attr
onfi_sync_opt_0
onfi_sync_opt_1
bch_cfg_0
bch_cfg_1
bch_cfg_2
bch_cfg_3
prot_regs Address Map
prot_regs Summary
prot_ctrl_0
prot_down_0
prot_up_0
prot_ctrl_1
prot_down_1
prot_up_1
rf_minictrl_regs Address Map
rf_minictrl_regs Summary
wp_settings
rbn_settings
common_settings
skip_bytes_conf
skip_bytes_offset
toggle_timings_0
toggle_timings_1
async_toggle_timings
sync_timings
timings0
timings1
timings2
dll_phy_update_cnt
dll_phy_ctrl
NAND_dataslice_Rfile Address Map
NAND_dataslice_Rfile Summary
phy_dq_timing_reg
phy_dqs_timing_reg
phy_gate_lpbk_ctrl_reg
phy_dll_master_ctrl_reg
phy_dll_slave_ctrl_reg
phy_ie_timing_reg
phy_obs_reg_0
phy_dll_obs_reg_0
phy_dll_obs_reg_1
phy_dll_obs_reg_2
phy_static_togg_reg
phy_wr_deskew_reg
phy_wr_rd_deskew_cmd_reg
phy_wr_deskew_pd_ctrl_0_reg
phy_wr_deskew_pd_ctrl_1_reg
phy_rd_deskew_reg
phy_version_reg
phy_features_reg
NAND_ctb_Rfile Address Map
NAND_ctb_Rfile Summary
phy_ctrl_reg
phy_tsel_reg
COMBOPHY Address Block Group
COMBOPHY_dataslice_Rfile Address Map
COMBOPHY_dataslice_Rfile Summary
phy_dq_timing_reg
phy_dqs_timing_reg
phy_gate_lpbk_ctrl_reg
phy_dll_master_ctrl_reg
phy_dll_slave_ctrl_reg
phy_ie_timing_reg
phy_obs_reg_0
phy_dll_obs_reg_0
phy_dll_obs_reg_1
phy_dll_obs_reg_2
phy_static_togg_reg
phy_wr_deskew_reg
phy_wr_rd_deskew_cmd_reg
phy_wr_deskew_pd_ctrl_0_reg
phy_wr_deskew_pd_ctrl_1_reg
phy_rd_deskew_reg
phy_version_reg
phy_features_reg
COMBOPHY_ctb_Rfile Address Map
COMBOPHY_ctb_Rfile Summary
phy_ctrl_reg
phy_tsel_reg
UART Address Block Group
UART1 Address Map
UART1 Summary
RBR
IER
IIR
LCR
MCR
LSR
MSR
SCR
SRBR0
SRBR1
SRBR2
SRBR3
SRBR4
SRBR5
SRBR6
SRBR7
SRBR8
SRBR9
SRBR10
SRBR11
SRBR12
SRBR13
SRBR14
SRBR15
FAR
TFR
RFW
USR
TFL
RFL
SRR
SRTS
SBCR
SDMAM
SFE
SRT
STET
HTX
DMASA
CPR
UCV
CTR
UART0 Address Map
UART0 Summary
RBR
IER
IIR
LCR
MCR
LSR
MSR
SCR
SRBR0
SRBR1
SRBR2
SRBR3
SRBR4
SRBR5
SRBR6
SRBR7
SRBR8
SRBR9
SRBR10
SRBR11
SRBR12
SRBR13
SRBR14
SRBR15
FAR
TFR
RFW
USR
TFL
RFL
SRR
SRTS
SBCR
SDMAM
SFE
SRT
STET
HTX
DMASA
CPR
UCV
CTR
I2C Address Block Group
i2c4_emac2 Address Map
i2c4_emac2 Summary
IC_CON
IC_TAR
IC_SAR
IC_DATA_CMD
IC_SS_SCL_HCNT
IC_SS_SCL_LCNT
IC_FS_SCL_HCNT
IC_FS_SCL_LCNT
IC_INTR_STAT
IC_INTR_MASK
IC_RAW_INTR_STAT
IC_RX_TL
IC_TX_TL
IC_CLR_INTR
IC_CLR_RX_UNDER
IC_CLR_RX_OVER
IC_CLR_TX_OVER
IC_CLR_RD_REQ
IC_CLR_TX_ABRT
IC_CLR_RX_DONE
IC_CLR_ACTIVITY
IC_CLR_STOP_DET
IC_CLR_START_DET
IC_CLR_GEN_CALL
IC_ENABLE
IC_STATUS
IC_TXFLR
IC_RXFLR
IC_SDA_HOLD
IC_TX_ABRT_SOURCE
IC_SLV_DATA_NACK_ONLY
IC_DMA_CR
IC_DMA_TDLR
IC_DMA_RDLR
IC_SDA_SETUP
IC_ACK_GENERAL_CALL
IC_ENABLE_STATUS
IC_FS_SPKLEN
IC_CLR_RESTART_DET
IC_COMP_PARAM_1
IC_COMP_VERSION
IC_COMP_TYPE
i2c3_emac1 Address Map
i2c3_emac1 Summary
IC_CON
IC_TAR
IC_SAR
IC_DATA_CMD
IC_SS_SCL_HCNT
IC_SS_SCL_LCNT
IC_FS_SCL_HCNT
IC_FS_SCL_LCNT
IC_INTR_STAT
IC_INTR_MASK
IC_RAW_INTR_STAT
IC_RX_TL
IC_TX_TL
IC_CLR_INTR
IC_CLR_RX_UNDER
IC_CLR_RX_OVER
IC_CLR_TX_OVER
IC_CLR_RD_REQ
IC_CLR_TX_ABRT
IC_CLR_RX_DONE
IC_CLR_ACTIVITY
IC_CLR_STOP_DET
IC_CLR_START_DET
IC_CLR_GEN_CALL
IC_ENABLE
IC_STATUS
IC_TXFLR
IC_RXFLR
IC_SDA_HOLD
IC_TX_ABRT_SOURCE
IC_SLV_DATA_NACK_ONLY
IC_DMA_CR
IC_DMA_TDLR
IC_DMA_RDLR
IC_SDA_SETUP
IC_ACK_GENERAL_CALL
IC_ENABLE_STATUS
IC_FS_SPKLEN
IC_CLR_RESTART_DET
IC_COMP_PARAM_1
IC_COMP_VERSION
IC_COMP_TYPE
i2c2_emac0 Address Map
i2c2_emac0 Summary
IC_CON
IC_TAR
IC_SAR
IC_DATA_CMD
IC_SS_SCL_HCNT
IC_SS_SCL_LCNT
IC_FS_SCL_HCNT
IC_FS_SCL_LCNT
IC_INTR_STAT
IC_INTR_MASK
IC_RAW_INTR_STAT
IC_RX_TL
IC_TX_TL
IC_CLR_INTR
IC_CLR_RX_UNDER
IC_CLR_RX_OVER
IC_CLR_TX_OVER
IC_CLR_RD_REQ
IC_CLR_TX_ABRT
IC_CLR_RX_DONE
IC_CLR_ACTIVITY
IC_CLR_STOP_DET
IC_CLR_START_DET
IC_CLR_GEN_CALL
IC_ENABLE
IC_STATUS
IC_TXFLR
IC_RXFLR
IC_SDA_HOLD
IC_TX_ABRT_SOURCE
IC_SLV_DATA_NACK_ONLY
IC_DMA_CR
IC_DMA_TDLR
IC_DMA_RDLR
IC_SDA_SETUP
IC_ACK_GENERAL_CALL
IC_ENABLE_STATUS
IC_FS_SPKLEN
IC_CLR_RESTART_DET
IC_COMP_PARAM_1
IC_COMP_VERSION
IC_COMP_TYPE
i2c1 Address Map
i2c1 Summary
IC_CON
IC_TAR
IC_SAR
IC_DATA_CMD
IC_SS_SCL_HCNT
IC_SS_SCL_LCNT
IC_FS_SCL_HCNT
IC_FS_SCL_LCNT
IC_INTR_STAT
IC_INTR_MASK
IC_RAW_INTR_STAT
IC_RX_TL
IC_TX_TL
IC_CLR_INTR
IC_CLR_RX_UNDER
IC_CLR_RX_OVER
IC_CLR_TX_OVER
IC_CLR_RD_REQ
IC_CLR_TX_ABRT
IC_CLR_RX_DONE
IC_CLR_ACTIVITY
IC_CLR_STOP_DET
IC_CLR_START_DET
IC_CLR_GEN_CALL
IC_ENABLE
IC_STATUS
IC_TXFLR
IC_RXFLR
IC_SDA_HOLD
IC_TX_ABRT_SOURCE
IC_SLV_DATA_NACK_ONLY
IC_DMA_CR
IC_DMA_TDLR
IC_DMA_RDLR
IC_SDA_SETUP
IC_ACK_GENERAL_CALL
IC_ENABLE_STATUS
IC_FS_SPKLEN
IC_CLR_RESTART_DET
IC_COMP_PARAM_1
IC_COMP_VERSION
IC_COMP_TYPE
i2c0 Address Map
i2c0 Summary
IC_CON
IC_TAR
IC_SAR
IC_DATA_CMD
IC_SS_SCL_HCNT
IC_SS_SCL_LCNT
IC_FS_SCL_HCNT
IC_FS_SCL_LCNT
IC_INTR_STAT
IC_INTR_MASK
IC_RAW_INTR_STAT
IC_RX_TL
IC_TX_TL
IC_CLR_INTR
IC_CLR_RX_UNDER
IC_CLR_RX_OVER
IC_CLR_TX_OVER
IC_CLR_RD_REQ
IC_CLR_TX_ABRT
IC_CLR_RX_DONE
IC_CLR_ACTIVITY
IC_CLR_STOP_DET
IC_CLR_START_DET
IC_CLR_GEN_CALL
IC_ENABLE
IC_STATUS
IC_TXFLR
IC_RXFLR
IC_SDA_HOLD
IC_TX_ABRT_SOURCE
IC_SLV_DATA_NACK_ONLY
IC_DMA_CR
IC_DMA_TDLR
IC_DMA_RDLR
IC_SDA_SETUP
IC_ACK_GENERAL_CALL
IC_ENABLE_STATUS
IC_FS_SPKLEN
IC_CLR_RESTART_DET
IC_COMP_PARAM_1
IC_COMP_VERSION
IC_COMP_TYPE
SPTIMER Address Block Group
SPTIMER1 Address Map
SPTIMER1 Summary
TIMER1LOADCOUNT
TIMER1CURRENTVAL
TIMER1CONTROLREG
TIMER1EOI
TIMER1INTSTAT
TIMERSINTSTAT
TIMERSEOI
TIMERSRAWINTSTAT
TIMERSCOMPVERSION
SPTIMER0 Address Map
SPTIMER0 Summary
TIMER1LOADCOUNT
TIMER1CURRENTVAL
TIMER1CONTROLREG
TIMER1EOI
TIMER1INTSTAT
TIMERSINTSTAT
TIMERSEOI
TIMERSRAWINTSTAT
TIMERSCOMPVERSION
GPIO Address Block Group
GPIO1 Address Map
GPIO1 Summary
GPIO_SWPORTA_DR
GPIO_SWPORTA_DDR
GPIO_INTEN
GPIO_INTMASK
GPIO_INTTYPE_LEVEL
GPIO_INT_POLARITY
GPIO_INTSTATUS
GPIO_RAW_INTSTATUS
GPIO_DEBOUNCE
GPIO_PORTA_EOI
GPIO_EXT_PORTA
GPIO_LS_SYNC
GPIO_ID_CODE
GPIO_VER_ID_CODE
GPIO_CONFIG_REG2
GPIO_CONFIG_REG1
GPIO0 Address Map
GPIO0 Summary
GPIO_SWPORTA_DR
GPIO_SWPORTA_DDR
GPIO_INTEN
GPIO_INTMASK
GPIO_INTTYPE_LEVEL
GPIO_INT_POLARITY
GPIO_INTSTATUS
GPIO_RAW_INTSTATUS
GPIO_DEBOUNCE
GPIO_PORTA_EOI
GPIO_EXT_PORTA
GPIO_LS_SYNC
GPIO_ID_CODE
GPIO_VER_ID_CODE
GPIO_CONFIG_REG2
GPIO_CONFIG_REG1
OSCTIMER Address Block Group
OSC1TIMER1 Address Map
OSC1TIMER1 Summary
TIMER1LOADCOUNT
TIMER1CURRENTVAL
TIMER1CONTROLREG
TIMER1EOI
TIMER1INTSTAT
TIMERSINTSTAT
TIMERSEOI
TIMERSRAWINTSTAT
TIMERSCOMPVERSION
OSC1TIMER0 Address Map
OSC1TIMER0 Summary
TIMER1LOADCOUNT
TIMER1CURRENTVAL
TIMER1CONTROLREG
TIMER1EOI
TIMER1INTSTAT
TIMERSINTSTAT
TIMERSEOI
TIMERSRAWINTSTAT
TIMERSCOMPVERSION
Watchdog_timer Address Block Group
WD4_csr Address Map
WD4_csr Summary
WDT_CR
WDT_TORR
WDT_CCVR
WDT_CRR
WDT_STAT
WDT_EOI
WDT_COMP_PARAM_1
WDT_COMP_VERSION
WDT_COMP_TYPE
WD3_csr Address Map
WD3_csr Summary
WDT_CR
WDT_TORR
WDT_CCVR
WDT_CRR
WDT_STAT
WDT_EOI
WDT_COMP_PARAM_1
WDT_COMP_VERSION
WDT_COMP_TYPE
WD2_csr Address Map
WD2_csr Summary
WDT_CR
WDT_TORR
WDT_CCVR
WDT_CRR
WDT_STAT
WDT_EOI
WDT_COMP_PARAM_1
WDT_COMP_VERSION
WDT_COMP_TYPE
WD1_csr Address Map
WD1_csr Summary
WDT_CR
WDT_TORR
WDT_CCVR
WDT_CRR
WDT_STAT
WDT_EOI
WDT_COMP_PARAM_1
WDT_COMP_VERSION
WDT_COMP_TYPE
WD0_csr Address Map
WD0_csr Summary
WDT_CR
WDT_TORR
WDT_CCVR
WDT_CRR
WDT_STAT
WDT_EOI
WDT_COMP_PARAM_1
WDT_COMP_VERSION
WDT_COMP_TYPE
Clock_Mgr Address Block Group
clkmgr Address Map
clkmgr Summary
ctrl
stat
testioctrl
intrgen
intrmsk
intrclr
intrsts
intrstk
intrraw
mainpllgrp Address Map
mainpllgrp Summary
en
ens
enr
bypass
bypasss
bypassr
nocclk
nocdiv
pllglob
fdbck
mem
memstat
vcocalib
pllc0
pllc1
pllc2
pllc3
pllm
fhop
ssc
lostlock
perpllgrp Address Map
perpllgrp Summary
en
ens
enr
bypass
bypasss
bypassr
emacctl
gpiodiv
pllglob
fdbck
mem
memstat
vcocalib
pllc0
pllc1
pllc2
pllc3
pllm
fhop
ssc
lostlock
ctlgrp Address Map
ctlgrp Summary
jtag
emacactr
emacbctr
emacptpctr
gpiodbctr
s2fuser0ctr
s2fuser1ctr
psirefctr
extcntrst
usb31ctr
dsuctr
core01ctr
core23ctr
core2ctr
core3ctr
serial_con_pll_ctr
Reset_Mgr Address Block Group
rstmgr Address Map
rstmgr Summary
stat
miscstat
hdsken
hdskreq
hdskack
hdskstall
per0modrst
per1modrst
brgmodrst
dbgmodrst
brgwarmmask
tststa
hdsktimeout
dbghdsktimeout
dbgrstcmplt
hpsrstcmplt
cpuinreset
cpurstrelease
cpu0_reset_base_low
cpu0_reset_base_high
cpu1_reset_base_low
cpu1_reset_base_high
cpu2_reset_base_low
cpu2_reset_base_high
cpu3_reset_base_low
cpu3_reset_base_high
System_Mgr Address Block Group
sysmgr Address Map
sysmgr Summary
siliconid1
siliconid2
wddbg
mpu_status
sdmmc_l3master
nand_l3master
usb0_l3master
usb1_l3master
tsn_global
tsn0
tsn1
tsn2
tsn0_ace
tsn1_ace
tsn2_ace
fpga_bridge_ctrl
fpgaintf_en_1
fpgaintf_en_2
fpgaintf_en_3
dmac0_l3master
etr_l3master
dmac1_l3master
sec_ctrl_slt
osc_trim
dmac0_ctrl_status_reg
dmac1_ctrl_status_reg
ecc_intmask_value
ecc_intmask_set
ecc_intmask_clr
ecc_intstatus_serr
ecc_intstatus_derr
noc_timeout
noc_idlestatus
fpga2soc_ctrl
fpga_config
gpo
gpi
mpu
sdm_hps_spare
hps_sdm_spare
dfi_interface_cfg
nand_dd_ctrl
nand_phy_ctrl_reg
nand_phy_tsel_reg
nand_phy_dq_timing_reg
phy_dqs_timing_reg
nand_phy_gate_lpbk_ctrl_reg
nand_phy_dll_master_ctrl_reg
nand_phy_dll_slave_ctrl_reg
nand_dd_default_setting_reg0
nand_dd_default_setting_reg1
nand_dd_status_reg
nand_dd_id_low_reg
nand_dd_id_high_reg
nand_write_prot_en_reg
sdmmc_cmd_queue_setting_reg
i3c_slv_pid_low
i3c_slv_pid_high
i3c_slv_ctrl_0
i3c_slv_ctrl_1
f2s_bridge_ctrl
dma_tbu_stash_ctrl_reg_0_dma0
dma_tbu_stash_ctrl_reg_0_dma1
sdm_tbu_stash_ctrl_reg_1_sdm
io_tbu_stash_ctrl_reg_2_usb2
io_tbu_stash_ctrl_reg_2_usb3
io_tbu_stash_ctrl_reg_2_sdmmc
io_tbu_stash_ctrl_reg_2_nand
io_tbu_stash_ctrl_reg_2_etr
tsn_tbu_stash_ctrl_reg_3_tsn0
tsn_tbu_stash_ctrl_reg_3_tsn1
tsn_tbu_stash_ctrl_reg_3_tsn2
dma_tbu_stream_ctrl_reg_0_dma0
dma_tbu_stream_ctrl_reg_0_dma1
sdm_tbu_stream_ctrl_reg_1_sdm
io_tbu_stream_ctrl_reg_2_usb2
io_tbu_stream_ctrl_reg_2_usb3
io_tbu_stream_ctrl_reg_2_sdmmc
io_tbu_stream_ctrl_reg_2_nand
io_tbu_stream_ctrl_reg_2_etr
tsn_tbu_stream_ctrl_reg_3_tsn0
tsn_tbu_stream_ctrl_reg_3_tsn1
tsn_tbu_stream_ctrl_reg_3_tsn2
dma_tbu_stream_id_Ax_reg_0_dma0
dma_tbu_stream_id_Ax_reg_0_dma1
sdm_tbu_stream_id_Ax_reg_1_sdm
io_tbu_stream_id_Ax_reg_2_usb2
io_tbu_stream_id_Ax_reg_2_usb3
io_tbu_stream_id_Ax_reg_2_sdmmc
io_tbu_stream_id_Ax_reg_2_nand
io_tbu_stream_id_Ax_reg_2_etr
tsn_tbu_stream_id_Ax_reg_3_tsn0
tsn_tbu_stream_id_Ax_reg_3_tsn1
tsn_tbu_stream_id_Ax_reg_3_tsn2
usb3_misc_ctrl_reg0
usb3_misc_ctrl_reg1
boot_scratch_cold0
boot_scratch_cold1
boot_scratch_cold2
boot_scratch_cold3
boot_scratch_cold4
boot_scratch_cold5
boot_scratch_cold6
boot_scratch_cold7
boot_scratch_cold8
boot_scratch_cold9
mpfe_config
mpfe_status
boot_scratch_warm0
boot_scratch_warm1
boot_scratch_warm2
boot_scratch_warm3
boot_scratch_warm4
boot_scratch_warm5
boot_scratch_warm6
boot_scratch_warm7
boot_scratch_warm8
boot_scratch_warm9
boot_scratch_por0
boot_scratch_por1
boot_scratch_por2
boot_scratch_por3
boot_scratch_por4
boot_scratch_por5
boot_scratch_por6
boot_scratch_por7
boot_scratch_por8
boot_scratch_por9
sdm_be_awaddr_remap
sdm_be_araddr_remap
Pin_Mux Address Block Group
pinmux Address Map
pinmux Summary
pin0sel
pin1sel
pin2sel
pin3sel
pin4sel
pin5sel
pin6sel
pin7sel
pin8sel
pin9sel
pin10sel
pin11sel
pin12sel
pin13sel
pin14sel
pin15sel
pin16sel
pin17sel
pin18sel
pin19sel
pin20sel
pin21sel
pin22sel
pin23sel
pin24sel
pin25sel
pin26sel
pin27sel
pin28sel
pin29sel
pin30sel
pin31sel
pin32sel
pin33sel
pin34sel
pin35sel
pin36sel
pin37sel
pin38sel
pin39sel
pin40sel
pin41sel
pin42sel
pin43sel
pin44sel
pin45sel
pin46sel
pin47sel
io0ctrl
io1ctrl
io2ctrl
io3ctrl
io4ctrl
io5ctrl
io6ctrl
io7ctrl
io8ctrl
io9ctrl
io10ctrl
io11ctrl
io12ctrl
io13ctrl
io14ctrl
io15ctrl
io16ctrl
io17ctrl
io18ctrl
io19ctrl
io20ctrl
io21ctrl
io22ctrl
io23ctrl
io24ctrl
io25ctrl
io26ctrl
io27ctrl
io28ctrl
io29ctrl
io30ctrl
io31ctrl
io32ctrl
io33ctrl
io34ctrl
io35ctrl
io36ctrl
io37ctrl
io38ctrl
io39ctrl
io40ctrl
io41ctrl
io42ctrl
io43ctrl
io44ctrl
io45ctrl
io46ctrl
io47ctrl
pinmux_emac0_usefpga
pinmux_emac1_usefpga
pinmux_emac2_usefpga
pinmux_i2c0_usefpga
pinmux_i2c1_usefpga
pinmux_i2c_emac0_usefpga
pinmux_i2c_emac1_usefpga
pinmux_i2c_emac2_usefpga
pinmux_spim0_usefpga
pinmux_spim1_usefpga
pinmux_spis0_usefpga
pinmux_spis1_usefpga
pinmux_uart0_usefpga
pinmux_uart1_usefpga
pinmux_mdio0_usefpga
pinmux_mdio1_usefpga
pinmux_mdio2_usefpga
pinmux_jtag_usefpga
io0_delay
io1_delay
io2_delay
io3_delay
io4_delay
io5_delay
io6_delay
io7_delay
io8_delay
io9_delay
io10_delay
io11_delay
io12_delay
io13_delay
io14_delay
io15_delay
io16_delay
io17_delay
io18_delay
io19_delay
io20_delay
io21_delay
io22_delay
io23_delay
io24_delay
io25_delay
io26_delay
io27_delay
io28_delay
io29_delay
io30_delay
io31_delay
io32_delay
io33_delay
io34_delay
io35_delay
io36_delay
io37_delay
io38_delay
io39_delay
io40_delay
io41_delay
io42_delay
io43_delay
io44_delay
io45_delay
io46_delay
io47_delay
pinmux_i3c0_usefpga
pinmux_i3c1_usefpga
L4_NOC_FW Address Block Group
tcu_scr Address Map
tcu_scr Summary
tcu
hps2fpga_scr Address Map
hps2fpga_scr Summary
soc2fpga
lwhps2fpga_scr Address Map
lwhps2fpga_scr Summary
lwsoc2fpga
L4_sys_scr Address Map
L4_sys_scr Summary
dma_ecc
emac0rx_ecc
emac0tx_ecc
emac1rx_ecc
emac1tx_ecc
emac2rx_ecc
emac2tx_ecc
nand_ecc
nand_read_ecc
nand_write_ecc
ocram_ecc
sdmmc_ecc
usb0_ecc
usb1_cacheecc
clock_manager
io_manager
reset_manager
system_manager
osc0_timer
osc1_timer
watchdog0
watchdog1
watchdog2
watchdog3
dap
watchdog4
power_manager
usb1_rxecc
usb1_txecc
l4_noc_probes
l4_noc_qos
L4_per_scr Address Map
L4_per_scr Summary
nand_register
usb0_register
usb1_register
spi_master0
spi_master1
spi_slave0
spi_slave1
emac0
emac1
emac2
sdmmc
gpio0
gpio1
i2c0
i2c1
i2c2
i2c3
i2c4
sp_timer0
sp_timer1
uart0
uart1
i3c0
i3c1
dma0
dma1
combo_phy
nand_sdma
L4_NOC_PRB Address Block Group
ccu_ios_obs_at_main_AtbEndPoint Address Map
ccu_ios_obs_at_main_AtbEndPoint Summary
cs_obs_at_main_AtbEndPoint_Id_CoreId
cs_obs_at_main_AtbEndPoint_Id_RevisionId
cs_obs_at_main_AtbEndPoint_AtbId
cs_obs_at_main_AtbEndPoint_AtbEn
ccu_ios_cs_obs_at_main_ErrorLogger_0 Address Map
ccu_ios_cs_obs_at_main_ErrorLogger_0 Summary
cs_obs_at_main_ErrorLogger_0_Id_CoreId
cs_obs_at_main_ErrorLogger_0_Id_RevisionId
cs_obs_at_main_ErrorLogger_0_FaultEn
cs_obs_at_main_ErrorLogger_0_ErrVld
cs_obs_at_main_ErrorLogger_0_ErrClr
cs_obs_at_main_ErrorLogger_0_ErrLog0
cs_obs_at_main_ErrorLogger_0_ErrLog1
cs_obs_at_main_ErrorLogger_0_ErrLog3
cs_obs_at_main_ErrorLogger_0_ErrLog4
cs_obs_at_main_ErrorLogger_0_ErrLog5
cs_obs_at_main_ErrorLogger_0_ErrLog6
cs_obs_at_main_ErrorLogger_0_ErrLog7
cs_obs_at_main_ErrorLogger_0_StallEn
ccu_ios_cs_obs_at_main_STPv2Converter Address Map
ccu_ios_cs_obs_at_main_STPv2Converter Summary
cs_obs_at_main_STPv2Converter_Id_CoreId
cs_obs_at_main_STPv2Converter_Id_RevisionId
cs_obs_at_main_STPv2Converter_AsyncPeriod
cs_obs_at_main_STPv2Converter_STPV2En
ccu_ios_probe_ccu_main_Probe Address Map
ccu_ios_probe_ccu_main_Probe Summary
probe_ccu_main_Probe_Id_CoreId
probe_ccu_main_Probe_Id_RevisionId
probe_ccu_main_Probe_MainCtl
probe_ccu_main_Probe_CfgCtl
probe_ccu_main_Probe_FilterLut
probe_ccu_main_Probe_TraceAlarmEn
probe_ccu_main_Probe_TraceAlarmStatus
probe_ccu_main_Probe_TraceAlarmClr
probe_ccu_main_Probe_StatPeriod
probe_ccu_main_Probe_StatGo
probe_ccu_main_Probe_StatAlarmMin
probe_ccu_main_Probe_StatAlarmMax
probe_ccu_main_Probe_StatAlarmStatus
probe_ccu_main_Probe_StatAlarmClr
probe_ccu_main_Probe_StatAlarmEn
probe_ccu_main_Probe_Filters_0_RouteIdBase
probe_ccu_main_Probe_Filters_0_RouteIdMask
probe_ccu_main_Probe_Filters_0_AddrBase_Low
probe_ccu_main_Probe_Filters_0_AddrBase_High
probe_ccu_main_Probe_Filters_0_WindowSize
probe_ccu_main_Probe_Filters_0_SecurityBase
probe_ccu_main_Probe_Filters_0_SecurityMask
probe_ccu_main_Probe_Filters_0_Opcode
probe_ccu_main_Probe_Filters_0_Status
probe_ccu_main_Probe_Filters_0_Length
probe_ccu_main_Probe_Filters_0_Urgency
probe_ccu_main_Probe_Filters_1_RouteIdBase
probe_ccu_main_Probe_Filters_1_RouteIdMask
probe_ccu_main_Probe_Filters_1_AddrBase_Low
probe_ccu_main_Probe_Filters_1_AddrBase_High
probe_ccu_main_Probe_Filters_1_WindowSize
probe_ccu_main_Probe_Filters_1_SecurityBase
probe_ccu_main_Probe_Filters_1_SecurityMask
probe_ccu_main_Probe_Filters_1_Opcode
probe_ccu_main_Probe_Filters_1_Status
probe_ccu_main_Probe_Filters_1_Length
probe_ccu_main_Probe_Filters_1_Urgency
probe_ccu_main_Probe_Counters_0_Src
probe_ccu_main_Probe_Counters_0_AlarmMode
probe_ccu_main_Probe_Counters_0_Val
probe_ccu_main_Probe_Counters_1_Src
probe_ccu_main_Probe_Counters_1_AlarmMode
probe_ccu_main_Probe_Counters_1_Val
probe_ccu_main_Probe_Counters_2_Src
probe_ccu_main_Probe_Counters_2_AlarmMode
probe_ccu_main_Probe_Counters_2_Val
probe_ccu_main_Probe_Counters_3_Src
probe_ccu_main_Probe_Counters_3_AlarmMode
probe_ccu_main_Probe_Counters_3_Val
ccu_ios_probe_emac_main_Probe Address Map
ccu_ios_probe_emac_main_Probe Summary
probe_emac_main_Probe_Id_CoreId
probe_emac_main_Probe_Id_RevisionId
probe_emac_main_Probe_MainCtl
probe_emac_main_Probe_CfgCtl
probe_emac_main_Probe_FilterLut
probe_emac_main_Probe_TraceAlarmEn
probe_emac_main_Probe_TraceAlarmStatus
probe_emac_main_Probe_TraceAlarmClr
probe_emac_main_Probe_StatPeriod
probe_emac_main_Probe_StatGo
probe_emac_main_Probe_StatAlarmMin
probe_emac_main_Probe_StatAlarmMax
probe_emac_main_Probe_StatAlarmStatus
probe_emac_main_Probe_StatAlarmClr
probe_emac_main_Probe_StatAlarmEn
probe_emac_main_Probe_Filters_0_RouteIdBase
probe_emac_main_Probe_Filters_0_RouteIdMask
probe_emac_main_Probe_Filters_0_AddrBase_Low
probe_emac_main_Probe_Filters_0_AddrBase_High
probe_emac_main_Probe_Filters_0_WindowSize
probe_emac_main_Probe_Filters_0_SecurityBase
probe_emac_main_Probe_Filters_0_SecurityMask
probe_emac_main_Probe_Filters_0_Opcode
probe_emac_main_Probe_Filters_0_Status
probe_emac_main_Probe_Filters_0_Length
probe_emac_main_Probe_Filters_0_Urgency
probe_emac_main_Probe_Filters_1_RouteIdBase
probe_emac_main_Probe_Filters_1_RouteIdMask
probe_emac_main_Probe_Filters_1_AddrBase_Low
probe_emac_main_Probe_Filters_1_AddrBase_High
probe_emac_main_Probe_Filters_1_WindowSize
probe_emac_main_Probe_Filters_1_SecurityBase
probe_emac_main_Probe_Filters_1_SecurityMask
probe_emac_main_Probe_Filters_1_Opcode
probe_emac_main_Probe_Filters_1_Status
probe_emac_main_Probe_Filters_1_Length
probe_emac_main_Probe_Filters_1_Urgency
probe_emac_main_Probe_Counters_0_Src
probe_emac_main_Probe_Counters_0_AlarmMode
probe_emac_main_Probe_Counters_0_Val
probe_emac_main_Probe_Counters_1_Src
probe_emac_main_Probe_Counters_1_AlarmMode
probe_emac_main_Probe_Counters_1_Val
probe_emac_main_Probe_Counters_2_Src
probe_emac_main_Probe_Counters_2_AlarmMode
probe_emac_main_Probe_Counters_2_Val
probe_emac_main_Probe_Counters_3_Src
probe_emac_main_Probe_Counters_3_AlarmMode
probe_emac_main_Probe_Counters_3_Val
ccu_ios_probe_soc2fpga_main_Probe Address Map
ccu_ios_probe_soc2fpga_main_Probe Summary
probe_soc2fpga_main_Probe_Id_CoreId
probe_soc2fpga_main_Probe_Id_RevisionId
probe_soc2fpga_main_Probe_MainCtl
probe_soc2fpga_main_Probe_CfgCtl
probe_soc2fpga_main_Probe_TracePortSel
probe_soc2fpga_main_Probe_FilterLut
probe_soc2fpga_main_Probe_TraceAlarmEn
probe_soc2fpga_main_Probe_TraceAlarmStatus
probe_soc2fpga_main_Probe_TraceAlarmClr
probe_soc2fpga_main_Probe_StatPeriod
probe_soc2fpga_main_Probe_StatGo
probe_soc2fpga_main_Probe_StatAlarmMin
probe_soc2fpga_main_Probe_StatAlarmMax
probe_soc2fpga_main_Probe_StatAlarmStatus
probe_soc2fpga_main_Probe_StatAlarmClr
probe_soc2fpga_main_Probe_StatAlarmEn
probe_soc2fpga_main_Probe_Filters_0_RouteIdBase
probe_soc2fpga_main_Probe_Filters_0_RouteIdMask
probe_soc2fpga_main_Probe_Filters_0_AddrBase_Low
probe_soc2fpga_main_Probe_Filters_0_AddrBase_High
probe_soc2fpga_main_Probe_Filters_0_WindowSize
probe_soc2fpga_main_Probe_Filters_0_SecurityBase
probe_soc2fpga_main_Probe_Filters_0_SecurityMask
probe_soc2fpga_main_Probe_Filters_0_Opcode
probe_soc2fpga_main_Probe_Filters_0_Status
probe_soc2fpga_main_Probe_Filters_0_Length
probe_soc2fpga_main_Probe_Filters_0_Urgency
probe_soc2fpga_main_Probe_Filters_1_RouteIdBase
probe_soc2fpga_main_Probe_Filters_1_RouteIdMask
probe_soc2fpga_main_Probe_Filters_1_AddrBase_Low
probe_soc2fpga_main_Probe_Filters_1_AddrBase_High
probe_soc2fpga_main_Probe_Filters_1_WindowSize
probe_soc2fpga_main_Probe_Filters_1_SecurityBase
probe_soc2fpga_main_Probe_Filters_1_SecurityMask
probe_soc2fpga_main_Probe_Filters_1_Opcode
probe_soc2fpga_main_Probe_Filters_1_Status
probe_soc2fpga_main_Probe_Filters_1_Length
probe_soc2fpga_main_Probe_Filters_1_Urgency
probe_soc2fpga_main_Probe_Counters_0_PortSel
probe_soc2fpga_main_Probe_Counters_0_Src
probe_soc2fpga_main_Probe_Counters_0_AlarmMode
probe_soc2fpga_main_Probe_Counters_0_Val
probe_soc2fpga_main_Probe_Counters_1_PortSel
probe_soc2fpga_main_Probe_Counters_1_Src
probe_soc2fpga_main_Probe_Counters_1_AlarmMode
probe_soc2fpga_main_Probe_Counters_1_Val
probe_soc2fpga_main_Probe_Counters_2_PortSel
probe_soc2fpga_main_Probe_Counters_2_Src
probe_soc2fpga_main_Probe_Counters_2_AlarmMode
probe_soc2fpga_main_Probe_Counters_2_Val
probe_soc2fpga_main_Probe_Counters_3_PortSel
probe_soc2fpga_main_Probe_Counters_3_Src
probe_soc2fpga_main_Probe_Counters_3_AlarmMode
probe_soc2fpga_main_Probe_Counters_3_Val
ccu_ios_probe_emac_main_TransactionStatProfiler Address Map
ccu_ios_probe_emac_main_TransactionStatProfiler Summary
probe_emac_main_TransactionStatProfiler_Id_CoreId
probe_emac_main_TransactionStatProfiler_Id_RevisionId
probe_emac_main_TransactionStatProfiler_En
probe_emac_main_TransactionStatProfiler_Mode
probe_emac_main_TransactionStatProfiler_Thresholds_0_0
probe_emac_main_TransactionStatProfiler_Thresholds_0_1
probe_emac_main_TransactionStatProfiler_Thresholds_0_2
probe_emac_main_TransactionStatProfiler_OverflowStatus
probe_emac_main_TransactionStatProfiler_OverflowReset
probe_emac_main_TransactionStatProfiler_PendingEventMode
probe_emac_main_TransactionStatProfiler_PreScaler
ccu_ios_probe_io_tbu_main_Probe Address Map
ccu_ios_probe_io_tbu_main_Probe Summary
probe_io_tbu_main_Probe_Id_CoreId
probe_io_tbu_main_Probe_Id_RevisionId
probe_io_tbu_main_Probe_MainCtl
probe_io_tbu_main_Probe_CfgCtl
probe_io_tbu_main_Probe_FilterLut
probe_io_tbu_main_Probe_TraceAlarmEn
probe_io_tbu_main_Probe_TraceAlarmStatus
probe_io_tbu_main_Probe_TraceAlarmClr
probe_io_tbu_main_Probe_StatPeriod
probe_io_tbu_main_Probe_StatGo
probe_io_tbu_main_Probe_StatAlarmMin
probe_io_tbu_main_Probe_StatAlarmMax
probe_io_tbu_main_Probe_StatAlarmStatus
probe_io_tbu_main_Probe_StatAlarmClr
probe_io_tbu_main_Probe_StatAlarmEn
probe_io_tbu_main_Probe_Filters_0_RouteIdBase
probe_io_tbu_main_Probe_Filters_0_RouteIdMask
probe_io_tbu_main_Probe_Filters_0_AddrBase_Low
probe_io_tbu_main_Probe_Filters_0_AddrBase_High
probe_io_tbu_main_Probe_Filters_0_WindowSize
probe_io_tbu_main_Probe_Filters_0_SecurityBase
probe_io_tbu_main_Probe_Filters_0_SecurityMask
probe_io_tbu_main_Probe_Filters_0_Opcode
probe_io_tbu_main_Probe_Filters_0_Status
probe_io_tbu_main_Probe_Filters_0_Length
probe_io_tbu_main_Probe_Filters_0_Urgency
probe_io_tbu_main_Probe_Filters_1_RouteIdBase
probe_io_tbu_main_Probe_Filters_1_RouteIdMask
probe_io_tbu_main_Probe_Filters_1_AddrBase_Low
probe_io_tbu_main_Probe_Filters_1_AddrBase_High
probe_io_tbu_main_Probe_Filters_1_WindowSize
probe_io_tbu_main_Probe_Filters_1_SecurityBase
probe_io_tbu_main_Probe_Filters_1_SecurityMask
probe_io_tbu_main_Probe_Filters_1_Opcode
probe_io_tbu_main_Probe_Filters_1_Status
probe_io_tbu_main_Probe_Filters_1_Length
probe_io_tbu_main_Probe_Filters_1_Urgency
probe_io_tbu_main_Probe_Counters_0_Src
probe_io_tbu_main_Probe_Counters_0_AlarmMode
probe_io_tbu_main_Probe_Counters_0_Val
probe_io_tbu_main_Probe_Counters_1_Src
probe_io_tbu_main_Probe_Counters_1_AlarmMode
probe_io_tbu_main_Probe_Counters_1_Val
probe_io_tbu_main_Probe_Counters_2_Src
probe_io_tbu_main_Probe_Counters_2_AlarmMode
probe_io_tbu_main_Probe_Counters_2_Val
probe_io_tbu_main_Probe_Counters_3_Src
probe_io_tbu_main_Probe_Counters_3_AlarmMode
probe_io_tbu_main_Probe_Counters_3_Val
ccu_ios_probe_io_tbu_main_TransactionStatProfiler Address Map
ccu_ios_probe_io_tbu_main_TransactionStatProfiler Summary
probe_io_tbu_main_TransactionStatProfiler_Id_CoreId
probe_io_tbu_main_TransactionStatProfiler_Id_RevisionId
probe_io_tbu_main_TransactionStatProfiler_En
probe_io_tbu_main_TransactionStatProfiler_Mode
probe_io_tbu_main_TransactionStatProfiler_Thresholds_0_0
probe_io_tbu_main_TransactionStatProfiler_Thresholds_0_1
probe_io_tbu_main_TransactionStatProfiler_Thresholds_0_2
probe_io_tbu_main_TransactionStatProfiler_OverflowStatus
probe_io_tbu_main_TransactionStatProfiler_OverflowReset
probe_io_tbu_main_TransactionStatProfiler_PendingEventMode
probe_io_tbu_main_TransactionStatProfiler_PreScaler
ccu_ios_ccu_ios_I_main_QosGenerator Address Map
ccu_ios_ccu_ios_I_main_QosGenerator Summary
ccu_ios_I_main_QosGenerator_Id_CoreId
ccu_ios_I_main_QosGenerator_Id_RevisionId
ccu_ios_I_main_QosGenerator_Priority
ccu_ios_I_main_QosGenerator_Mode
ccu_ios_I_main_QosGenerator_Bandwidth
ccu_ios_I_main_QosGenerator_Saturation
ccu_ios_I_main_QosGenerator_ExtControl
ccu_ios_dma_tbu_m_I_main_QosGenerator Address Map
ccu_ios_dma_tbu_m_I_main_QosGenerator Summary
dma_tbu_m_I_main_QosGenerator_Id_CoreId
dma_tbu_m_I_main_QosGenerator_Id_RevisionId
dma_tbu_m_I_main_QosGenerator_Priority
dma_tbu_m_I_main_QosGenerator_Mode
dma_tbu_m_I_main_QosGenerator_Bandwidth
dma_tbu_m_I_main_QosGenerator_Saturation
dma_tbu_m_I_main_QosGenerator_ExtControl
ccu_ios_emac_tbu_m_I_main_QosGenerator Address Map
ccu_ios_emac_tbu_m_I_main_QosGenerator Summary
emac_tbu_m_I_main_QosGenerator_Id_CoreId
emac_tbu_m_I_main_QosGenerator_Id_RevisionId
emac_tbu_m_I_main_QosGenerator_Priority
emac_tbu_m_I_main_QosGenerator_Mode
emac_tbu_m_I_main_QosGenerator_Bandwidth
emac_tbu_m_I_main_QosGenerator_Saturation
emac_tbu_m_I_main_QosGenerator_ExtControl
ccu_ios_io_tbu_m_I_main_QosGenerator Address Map
ccu_ios_io_tbu_m_I_main_QosGenerator Summary
io_tbu_m_I_main_QosGenerator_Id_CoreId
io_tbu_m_I_main_QosGenerator_Id_RevisionId
io_tbu_m_I_main_QosGenerator_Priority
io_tbu_m_I_main_QosGenerator_Mode
io_tbu_m_I_main_QosGenerator_Bandwidth
io_tbu_m_I_main_QosGenerator_Saturation
io_tbu_m_I_main_QosGenerator_ExtControl
ccu_ios_sdm_tbu_m_I_main_QosGenerator Address Map
ccu_ios_sdm_tbu_m_I_main_QosGenerator Summary
sdm_tbu_m_I_main_QosGenerator_Id_CoreId
sdm_tbu_m_I_main_QosGenerator_Id_RevisionId
sdm_tbu_m_I_main_QosGenerator_Priority
sdm_tbu_m_I_main_QosGenerator_Mode
sdm_tbu_m_I_main_QosGenerator_Bandwidth
sdm_tbu_m_I_main_QosGenerator_Saturation
sdm_tbu_m_I_main_QosGenerator_ExtControl
ccu_ios_emac_tbu_m_I_main_TransactionStatFilter Address Map
ccu_ios_emac_tbu_m_I_main_TransactionStatFilter Summary
emac_tbu_m_I_main_TransactionStatFilter_Id_CoreId
emac_tbu_m_I_main_TransactionStatFilter_Id_RevisionId
emac_tbu_m_I_main_TransactionStatFilter_Mode
emac_tbu_m_I_main_TransactionStatFilter_AddrBase_Low
emac_tbu_m_I_main_TransactionStatFilter_AddrBase_High
emac_tbu_m_I_main_TransactionStatFilter_AddrWindowSize
emac_tbu_m_I_main_TransactionStatFilter_Opcode
emac_tbu_m_I_main_TransactionStatFilter_UserBase
emac_tbu_m_I_main_TransactionStatFilter_UserMask
emac_tbu_m_I_main_TransactionStatFilter_SecurityBase
emac_tbu_m_I_main_TransactionStatFilter_SecurityMask
emac_tbu_m_I_main_TransactionStatFilter_UserBaseHigh
emac_tbu_m_I_main_TransactionStatFilter_UserMaskHigh
ccu_ios_io_tbu_m_I_main_TransactionStatFilter Address Map
ccu_ios_io_tbu_m_I_main_TransactionStatFilter Summary
io_tbu_m_I_main_TransactionStatFilter_Id_CoreId
io_tbu_m_I_main_TransactionStatFilter_Id_RevisionId
io_tbu_m_I_main_TransactionStatFilter_Mode
io_tbu_m_I_main_TransactionStatFilter_AddrBase_Low
io_tbu_m_I_main_TransactionStatFilter_AddrBase_High
io_tbu_m_I_main_TransactionStatFilter_AddrWindowSize
io_tbu_m_I_main_TransactionStatFilter_Opcode
io_tbu_m_I_main_TransactionStatFilter_UserBase
io_tbu_m_I_main_TransactionStatFilter_UserMask
io_tbu_m_I_main_TransactionStatFilter_SecurityBase
io_tbu_m_I_main_TransactionStatFilter_SecurityMask
io_tbu_m_I_main_TransactionStatFilter_UserBaseHigh
io_tbu_m_I_main_TransactionStatFilter_UserMaskHigh
I3C Address Block Group
i3c_secondary_master Address Map
i3c_secondary_master Summary
DEVICE_CTRL
DEVICE_ADDR
HW_CAPABILITY
COMMAND_QUEUE_PORT
RESPONSE_QUEUE_PORT
TX_DATA_PORT
IBI_QUEUE_STATUS
QUEUE_THLD_CTRL
DATA_BUFFER_THLD_CTRL
IBI_QUEUE_CTRL
IBI_MR_REQ_REJECT
IBI_SIR_REQ_REJECT
RESET_CTRL
SLV_EVENT_STATUS
INTR_STATUS
INTR_STATUS_EN
INTR_SIGNAL_EN
INTR_FORCE
QUEUE_STATUS_LEVEL
DATA_BUFFER_STATUS_LEVEL
PRESENT_STATE
CCC_DEVICE_STATUS
DEVICE_ADDR_TABLE_POINTER
DEV_CHAR_TABLE_POINTER
VENDOR_SPECIFIC_REG_POINTER
SLV_MIPI_ID_VALUE
SLV_PID_VALUE
SLV_CHAR_CTRL
SLV_MAX_LEN
MAX_READ_TURNAROUND
MAX_DATA_SPEED
SLV_INTR_REQ
DEVICE_CTRL_EXTENDED
SCL_I3C_OD_TIMING
SCL_I3C_PP_TIMING
SCL_I2C_FM_TIMING
SCL_I2C_FMP_TIMING
SCL_EXT_LCNT_TIMING
SCL_EXT_TERMN_LCNT_TIMING
SDA_HOLD_SWITCH_DLY_TIMING
BUS_FREE_AVAIL_TIMING
BUS_IDLE_TIMING
I3C_VER_ID
I3C_VER_TYPE
QUEUE_SIZE_CAPABILITY
DEV_CHAR_TABLE1_LOC1
DEV_CHAR_TABLE1_LOC2
DEV_CHAR_TABLE1_LOC3
DEV_CHAR_TABLE1_LOC4
DEV_CHAR_TABLE2_LOC1
DEV_CHAR_TABLE2_LOC2
DEV_CHAR_TABLE2_LOC3
DEV_CHAR_TABLE2_LOC4
DEV_CHAR_TABLE3_LOC1
DEV_CHAR_TABLE3_LOC2
DEV_CHAR_TABLE3_LOC3
DEV_CHAR_TABLE3_LOC4
DEV_CHAR_TABLE4_LOC1
DEV_CHAR_TABLE4_LOC2
DEV_CHAR_TABLE4_LOC3
DEV_CHAR_TABLE4_LOC4
DEV_CHAR_TABLE5_LOC1
DEV_CHAR_TABLE5_LOC2
DEV_CHAR_TABLE5_LOC3
DEV_CHAR_TABLE5_LOC4
DEV_CHAR_TABLE6_LOC1
DEV_CHAR_TABLE6_LOC2
DEV_CHAR_TABLE6_LOC3
DEV_CHAR_TABLE6_LOC4
DEV_CHAR_TABLE7_LOC1
DEV_CHAR_TABLE7_LOC2
DEV_CHAR_TABLE7_LOC3
DEV_CHAR_TABLE7_LOC4
DEV_CHAR_TABLE8_LOC1
DEV_CHAR_TABLE8_LOC2
DEV_CHAR_TABLE8_LOC3
DEV_CHAR_TABLE8_LOC4
DEV_ADDR_TABLE_LOC1
DEV_ADDR_TABLE_LOC2
DEV_ADDR_TABLE_LOC3
DEV_ADDR_TABLE_LOC4
DEV_ADDR_TABLE_LOC5
DEV_ADDR_TABLE_LOC6
DEV_ADDR_TABLE_LOC7
DEV_ADDR_TABLE_LOC8
DEV_ADDR_TABLE_LOC9
DEV_ADDR_TABLE_LOC10
DEV_ADDR_TABLE_LOC11
i3c_main_master Address Map
i3c_main_master Summary
DEVICE_CTRL
DEVICE_ADDR
HW_CAPABILITY
COMMAND_QUEUE_PORT
RESPONSE_QUEUE_PORT
TX_DATA_PORT
IBI_QUEUE_STATUS
QUEUE_THLD_CTRL
DATA_BUFFER_THLD_CTRL
IBI_QUEUE_CTRL
RESET_CTRL
SLV_EVENT_STATUS
INTR_STATUS
INTR_STATUS_EN
INTR_SIGNAL_EN
INTR_FORCE
QUEUE_STATUS_LEVEL
DATA_BUFFER_STATUS_LEVEL
PRESENT_STATE
DEVICE_ADDR_TABLE_POINTER
DEV_CHAR_TABLE_POINTER
VENDOR_SPECIFIC_REG_POINTER
DEVICE_CTRL_EXTENDED
SCL_I3C_OD_TIMING
SCL_I3C_PP_TIMING
SCL_I2C_FM_TIMING
SCL_I2C_FMP_TIMING
SCL_EXT_LCNT_TIMING
SCL_EXT_TERMN_LCNT_TIMING
SDA_HOLD_SWITCH_DLY_TIMING
BUS_FREE_AVAIL_TIMING
I3C_VER_ID
I3C_VER_TYPE
QUEUE_SIZE_CAPABILITY
DEV_CHAR_TABLE1_LOC1
DEV_CHAR_TABLE1_LOC2
DEV_CHAR_TABLE1_LOC3
DEV_CHAR_TABLE1_LOC4
DEV_CHAR_TABLE2_LOC1
DEV_CHAR_TABLE2_LOC2
DEV_CHAR_TABLE2_LOC3
DEV_CHAR_TABLE2_LOC4
DEV_CHAR_TABLE3_LOC1
DEV_CHAR_TABLE3_LOC2
DEV_CHAR_TABLE3_LOC3
DEV_CHAR_TABLE3_LOC4
DEV_CHAR_TABLE4_LOC1
DEV_CHAR_TABLE4_LOC2
DEV_CHAR_TABLE4_LOC3
DEV_CHAR_TABLE4_LOC4
DEV_CHAR_TABLE5_LOC1
DEV_CHAR_TABLE5_LOC2
DEV_CHAR_TABLE5_LOC3
DEV_CHAR_TABLE5_LOC4
DEV_CHAR_TABLE6_LOC1
DEV_CHAR_TABLE6_LOC2
DEV_CHAR_TABLE6_LOC3
DEV_CHAR_TABLE6_LOC4
DEV_CHAR_TABLE7_LOC1
DEV_CHAR_TABLE7_LOC2
DEV_CHAR_TABLE7_LOC3
DEV_CHAR_TABLE7_LOC4
DEV_CHAR_TABLE8_LOC1
DEV_CHAR_TABLE8_LOC2
DEV_CHAR_TABLE8_LOC3
DEV_CHAR_TABLE8_LOC4
DEV_ADDR_TABLE1_LOC1
DEV_ADDR_TABLE2_LOC1
DEV_ADDR_TABLE3_LOC1
DEV_ADDR_TABLE4_LOC1
DEV_ADDR_TABLE5_LOC1
DEV_ADDR_TABLE6_LOC1
DEV_ADDR_TABLE7_LOC1
DEV_ADDR_TABLE8_LOC1
DEV_ADDR_TABLE9_LOC1
DEV_ADDR_TABLE10_LOC1
DEV_ADDR_TABLE11_LOC1
SPI Address Block Group
SPIS_1 Address Map
SPIS_1 Summary
CTRLR0
SSIENR
MWCR
TXFTLR
RXFTLR
TXFLR
RXFLR
SR
IMR
ISR
RISR
TXOICR
RXOICR
RXUICR
MSTICR
ICR
DMACR
DMATDLR
DMARDLR
IDR
SSI_VERSION_ID
DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7
DR8
DR9
DR10
DR11
DR12
DR13
DR14
DR15
DR16
DR17
DR18
DR19
DR20
DR21
DR22
DR23
DR24
DR25
DR26
DR27
DR28
DR29
DR30
DR31
DR32
DR33
DR34
DR35
RSVD_1
RSVD_2
SPIS_0 Address Map
SPIS_0 Summary
CTRLR0
SSIENR
MWCR
TXFTLR
RXFTLR
TXFLR
RXFLR
SR
IMR
ISR
RISR
TXOICR
RXOICR
RXUICR
MSTICR
ICR
DMACR
DMATDLR
DMARDLR
IDR
SSI_VERSION_ID
DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7
DR8
DR9
DR10
DR11
DR12
DR13
DR14
DR15
DR16
DR17
DR18
DR19
DR20
DR21
DR22
DR23
DR24
DR25
DR26
DR27
DR28
DR29
DR30
DR31
DR32
DR33
DR34
DR35
RSVD_1
RSVD_2
SPIM_1 Address Map
SPIM_1 Summary
CTRLR0
CTRLR1
SSIENR
MWCR
SER
BAUDR
TXFTLR
RXFTLR
TXFLR
RXFLR
SR
IMR
ISR
RISR
TXOICR
RXOICR
RXUICR
MSTICR
ICR
DMACR
DMATDLR
DMARDLR
IDR
SSI_VERSION_ID
DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7
DR8
DR9
DR10
DR11
DR12
DR13
DR14
DR15
DR16
DR17
DR18
DR19
DR20
DR21
DR22
DR23
DR24
DR25
DR26
DR27
DR28
DR29
DR30
DR31
DR32
DR33
DR34
DR35
RX_SAMPLE_DLY
RSVD_1
RSVD_2
SPIM_0 Address Map
SPIM_0 Summary
CTRLR0
CTRLR1
SSIENR
MWCR
SER
BAUDR
TXFTLR
RXFTLR
TXFLR
RXFLR
SR
IMR
ISR
RISR
TXOICR
RXOICR
RXUICR
MSTICR
ICR
DMACR
DMATDLR
DMARDLR
IDR
SSI_VERSION_ID
DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7
DR8
DR9
DR10
DR11
DR12
DR13
DR14
DR15
DR16
DR17
DR18
DR19
DR20
DR21
DR22
DR23
DR24
DR25
DR26
DR27
DR28
DR29
DR30
DR31
DR32
DR33
DR34
DR35
RX_SAMPLE_DLY
RSVD_1
RSVD_2
DMAC0 Address Block Group
DMAC0_Common Address Map
DMAC0_Common Summary
DMAC_IDREG
DMAC_COMPVERREG
DMAC_CFGREG
DMAC_CHENREG
DMAC_INTSTATUSREG
DMAC_COMMONREG_INTCLEARREG
DMAC_COMMONREG_INTSTATUS_ENABLEREG
DMAC_COMMONREG_INTSIGNAL_ENABLEREG
DMAC_COMMONREG_INTSTATUSREG
DMAC_RESETREG
DMAC_LOWPOWER_CFGREG
DMAC0_Channel1 Address Map
DMAC0_Channel1 Summary
CH1_SAR
CH1_DAR
CH1_BLOCK_TS
CH1_CTL
CH1_CFG2
CH1_LLP
CH1_STATUSREG
CH1_SWHSSRCREG
CH1_SWHSDSTREG
CH1_BLK_TFR_RESUMEREQREG
CH1_AXI_IDREG
CH1_AXI_QOSREG
CH1_INTSTATUS_ENABLEREG
CH1_INTSTATUS
CH1_INTSIGNAL_ENABLEREG
CH1_INTCLEARREG
DMAC0_Channel2 Address Map
DMAC0_Channel2 Summary
CH2_SAR
CH2_DAR
CH2_BLOCK_TS
CH2_CTL
CH2_CFG2
CH2_LLP
CH2_STATUSREG
CH2_SWHSSRCREG
CH2_SWHSDSTREG
CH2_BLK_TFR_RESUMEREQREG
CH2_AXI_IDREG
CH2_AXI_QOSREG
CH2_INTSTATUS_ENABLEREG
CH2_INTSTATUS
CH2_INTSIGNAL_ENABLEREG
CH2_INTCLEARREG
DMAC0_Channel3 Address Map
DMAC0_Channel3 Summary
CH3_SAR
CH3_DAR
CH3_BLOCK_TS
CH3_CTL
CH3_CFG2
CH3_LLP
CH3_STATUSREG
CH3_SWHSSRCREG
CH3_SWHSDSTREG
CH3_BLK_TFR_RESUMEREQREG
CH3_AXI_IDREG
CH3_AXI_QOSREG
CH3_INTSTATUS_ENABLEREG
CH3_INTSTATUS
CH3_INTSIGNAL_ENABLEREG
CH3_INTCLEARREG
DMAC0_Channel4 Address Map
DMAC0_Channel4 Summary
CH4_SAR
CH4_DAR
CH4_BLOCK_TS
CH4_CTL
CH4_CFG2
CH4_LLP
CH4_STATUSREG
CH4_SWHSSRCREG
CH4_SWHSDSTREG
CH4_BLK_TFR_RESUMEREQREG
CH4_AXI_IDREG
CH4_AXI_QOSREG
CH4_INTSTATUS_ENABLEREG
CH4_INTSTATUS
CH4_INTSIGNAL_ENABLEREG
CH4_INTCLEARREG
DMAC0_RESERVED Address Map
DMAC1 Address Block Group
DMAC1_Common Address Map
DMAC1_Common Summary
DMAC_IDREG
DMAC_COMPVERREG
DMAC_CFGREG
DMAC_CHENREG
DMAC_INTSTATUSREG
DMAC_COMMONREG_INTCLEARREG
DMAC_COMMONREG_INTSTATUS_ENABLEREG
DMAC_COMMONREG_INTSIGNAL_ENABLEREG
DMAC_COMMONREG_INTSTATUSREG
DMAC_RESETREG
DMAC_LOWPOWER_CFGREG
DMAC1_Channel1 Address Map
DMAC1_Channel1 Summary
CH1_SAR
CH1_DAR
CH1_BLOCK_TS
CH1_CTL
CH1_CFG2
CH1_LLP
CH1_STATUSREG
CH1_SWHSSRCREG
CH1_SWHSDSTREG
CH1_BLK_TFR_RESUMEREQREG
CH1_AXI_IDREG
CH1_AXI_QOSREG
CH1_INTSTATUS_ENABLEREG
CH1_INTSTATUS
CH1_INTSIGNAL_ENABLEREG
CH1_INTCLEARREG
DMAC1_Channel2 Address Map
DMAC1_Channel2 Summary
CH2_SAR
CH2_DAR
CH2_BLOCK_TS
CH2_CTL
CH2_CFG2
CH2_LLP
CH2_STATUSREG
CH2_SWHSSRCREG
CH2_SWHSDSTREG
CH2_BLK_TFR_RESUMEREQREG
CH2_AXI_IDREG
CH2_AXI_QOSREG
CH2_INTSTATUS_ENABLEREG
CH2_INTSTATUS
CH2_INTSIGNAL_ENABLEREG
CH2_INTCLEARREG
DMAC1_Channel3 Address Map
DMAC1_Channel3 Summary
CH3_SAR
CH3_DAR
CH3_BLOCK_TS
CH3_CTL
CH3_CFG2
CH3_LLP
CH3_STATUSREG
CH3_SWHSSRCREG
CH3_SWHSDSTREG
CH3_BLK_TFR_RESUMEREQREG
CH3_AXI_IDREG
CH3_AXI_QOSREG
CH3_INTSTATUS_ENABLEREG
CH3_INTSTATUS
CH3_INTSIGNAL_ENABLEREG
CH3_INTCLEARREG
DMAC1_Channel4 Address Map
DMAC1_Channel4 Summary
CH4_SAR
CH4_DAR
CH4_BLOCK_TS
CH4_CTL
CH4_CFG2
CH4_LLP
CH4_STATUSREG
CH4_SWHSSRCREG
CH4_SWHSDSTREG
CH4_BLK_TFR_RESUMEREQREG
CH4_AXI_IDREG
CH4_AXI_QOSREG
CH4_INTSTATUS_ENABLEREG
CH4_INTSTATUS
CH4_INTSIGNAL_ENABLEREG
CH4_INTCLEARREG
DMAC1_RESERVED Address Map
USB3.1 Address Block Group
DWC_usb31_block_eXtensible_Host_Cntrl_Cap_Regs Address Map
DWC_usb31_block_eXtensible_Host_Cntrl_Cap_Regs Summary
CAPLENGTH
HCSPARAMS1
HCSPARAMS2
HCSPARAMS3
HCCPARAMS1
DBOFF
RTSOFF
HCCPARAMS2
DWC_usb31_block_Host_Cntrl_Oper_Regs Address Map
DWC_usb31_block_Host_Cntrl_Oper_Regs Summary
USBCMD
USBSTS
PAGESIZE
DNCTRL
CRCR_LO
CRCR_HI
DCBAAP_LO
DCBAAP_HI
CONFIG
DWC_usb31_block_Host_Cntrl_Port_Reg_Set Address Map
PORTSC_20_REGS
PORTSC_20
PORTPMSC_20
PORTLI_20
PORTHLPMC_20
PORTSC_30_REGS
PORTSC_30
PORTPMSC_30
PORTLI_30
PORTHLPMC_30
DWC_usb31_block_HC_Extended_Capability_Register Address Map
DWC_usb31_block_HC_Extended_Capability_Register Summary
USBLEGSUP
USBLEGCTLSTS
DWC_usb31_block_xHCI_Supt_USB20_Prt_Cap Address Map
DWC_usb31_block_xHCI_Supt_USB20_Prt_Cap Summary
SUPTPRT2_DW0
SUPTPRT2_DW1
SUPTPRT2_DW2
SUPTPRT2_DW3
DWC_usb31_block_xHCI_Supt_USB30_Prt_Cap Address Map
SUPT_30_REGS
SUPTPRT3_DW0
SUPTPRT3_DW1
SUPTPRT3_DW2
SUPTPRT3_DW3
SUPTPRT3_DW4
SUPTPRT3_DW5
SUPTPRT3_DW6
SUPTPRT3_DW7
DWC_usb31_block_Debug_Capability_Structure Address Map
DWC_usb31_block_Debug_Capability_Structure Summary
DCID
DCDB
DCERSTSZ
RSVD0
DCERSTBA_LO
DCERSTBA_HI
DCERDP_LO
DCERDP_HI
DCCTRL
DCST
DCPORTSC
RSVD1
DCCP_LO
DCCP_HI
DCDDI1
DCDDI2
DWC_usb31_block_Host_Cntrl_Runtime_Regs Address Map
DWC_usb31_block_Host_Cntrl_Runtime_Regs Summary
MFINDEX
RsvdZ
DWC_usb31_block_Interrupter_Regs Address Map
IMAN_REGS
IMAN
IMOD
ERSTSZ
RsvdP
ERSTBA_LO
ERSTBA_HI
ERDP_LO
ERDP_HI
DWC_usb31_block_Doorbell_Register Address Map
DB_REGS
DB
DWC_usb31_block_gbl Address Map
GUSB2PHYCFG_REGS
GUSB2PHYCFG
GUSB2PHYACC_REGS
GUSB2PHYACC_ULPI
GUSB3PIPECTL_REGS
GUSB3PIPECTL
GTXFIFOSIZ_REGS
GTXFIFOSIZ0
GTXFIFOSIZ1
GTXFIFOSIZ2
GTXFIFOSIZ3
GTXFIFOSIZ4
GTXFIFOSIZ5
GTXFIFOSIZ6
GTXFIFOSIZ7
GTXFIFOSIZ8
GTXFIFOSIZ9
GTXFIFOSIZ10
GTXFIFOSIZ11
GTXFIFOSIZ12
GTXFIFOSIZ13
GTXFIFOSIZ14
GTXFIFOSIZ15
GRXFIFOSIZ_REGS
GRXFIFOSIZ0
GRXFIFOSIZ1
GRXFIFOSIZ2
GRXFIFOSIZ3
GRXFIFOSIZ4
GRXFIFOSIZ5
GEVNTADRLO_REGS
GEVNTADRLO
GEVNTADRHI
GEVNTSIZ
GEVNTCOUNT
GUSB2RHBCTL_REGS
GUSB2RHBCTL
DWC_usb31_block_gbl Summary
GSBUSCFG0
GSBUSCFG1
GTXTHRCFG
GRXTHRCFG
GCTL
GPMSTS
GSTS
GUCTL1
USB31_IP_NAME
GGPIO
GUID
GUCTL
GBUSERRADDRLO
GBUSERRADDRHI
GPRTBIMAPLO
GPRTBIMAPHI
GHWPARAMS0
GHWPARAMS1
GHWPARAMS2
GHWPARAMS3
GHWPARAMS4
GHWPARAMS5
GHWPARAMS6
GHWPARAMS7
GDBGFIFOSPACE
GBMUCTL
GDBGBMU
GDBGLSPMUX
GDBGLSP
GDBGEPINFO0
GDBGEPINFO1
GPRTBIMAP_HSLO
GPRTBIMAP_HSHI
GPRTBIMAP_FSLO
GPRTBIMAP_FSHI
GHMSOCBWOR
USB31_VER_NUMBER
USB31_VER_TYPE
GSYSBLKWINCTRL
GPCIEL1EXTLAT
GHWPARAMS8
GSMACCTL
GUCTL2
GUCTL3
GTXFIFOPRIDEV
GTXFIFOPRIHST
GRXFIFOPRIHST
GFIFOPRIDBC
GDMAHLRATIO
GOSTDDMA_ASYNC
GOSTDDMA_PRD
GFLADJ
GUCTL4
GUCTL5
DWC_usb31_block_dev Address Map
Rsvd_REGS
Rsvd
DEPCMDPAR2_REGS
DEPCMDPAR2
DEPCMDPAR1
DEPCMDPAR0
DEPCMD
DEV_IMOD_REGS
DEV_IMOD
DWC_usb31_block_dev Summary
DCFG
DCTL
DEVTEN
DSTS
DGCMDPAR
DGCMD
DCTL1
DALEPENA
DLDMENA
DWC_usb31_block_rsvd0 Address Map
DWC_usb31_block_rsvd0 Summary
rsvd0_reg
DWC_usb31_block_link Address Map
LINK_REGS
LU1LFPSRXTIM
LU1LFPSTXTIM
LU2LFPSRXTIM
LU2LFPSTXTIM
LU3LFPSRXTIM
LU3LFPSTXTIM
LPINGLFPSTIM
LPOLLLFPSTXTIM
LSKIPFREQ
LLUCTL
LPTMDPDELAY
LSCDTIM1
LSCDTIM2
LSCDTIM3
LSCDTIM4
LLPBMTIM1
LLPBMTIM2
LLPBMTXTIM
LLINKERRINJ
LLINKERRINJEN
GDBGLTSSM
GDBGLNMCC
LLINKDBGCTRL
LLINKDBGCNTTRIG
LCSR_TX_DEEMPH
LCSR_TX_DEEMPH_1
LCSR_TX_DEEMPH_2
LCSR_TX_DEEMPH_3
LCSRPTMDEBUG1
LCSRPTMDEBUG2
LPTMDPDELAY2
DWC_usb31_block_debug Address Map
RHBDBG_REGS
BU31RHBDBG
DWC_usb31_block_debug Summary
BRAMHIADDR
BRSERRCNT
BRMERRCNT
BRAMECCERR
BRERRCTL
BRAM0ADDRERR
BRAM1ADDRERR
BRAM2ADDRERR
BRAM3ADDRERR
BRAM4ADDRERR
BLOOPBCKCTRL
BLOOPBCKTFERSZ
BBISTDATAPATSEED
BBISTCTRL
BBISTXFERSTS0
BBISTXFERSTS1
BBISTXFERSTS2
BBISTXFERSTS3
BBISTEXPDATASTS0
BBISTEXPDATASTS1
BBISTEXPDATASTS2
BBISTEXPDATASTS3
BBISTRCVDDATASTS0
BBISTRCVDDATASTS1
BBISTRCVDDATASTS2
BBISTRCVDDATASTS3
DWC_usb31_block_rsvd Address Map
DWC_usb31_block_rsvd Summary
rsvd_reg
SMMU_and_TCU Address Block Group
smmu_tcu Address Map
smmu_tcu Summary
SMMU_IDR0
SMMU_IDR1
SMMU_IDR2
SMMU_IDR3
SMMU_IDR5
SMMU_IIDR
SMMU_AIDR
SMMU_CR0
SMMU_CR0ACK
SMMU_CR1
SMMU_CR2
SMMU_GBPA
SMMU_IRQ_CTRL
SMMU_IRQ_CTRLACK
SMMU_GERROR
SMMU_GERRORN
SMMU_GERROR_IRQ_CFG0_LO
SMMU_GERROR_IRQ_CFG0_HI
SMMU_GERROR_IRQ_CFG1
SMMU_GERROR_IRQ_CFG2
SMMU_STRTAB_BASE_LO
SMMU_STRTAB_BASE_HI
SMMU_STRTAB_BASE_CFG
SMMU_CMDQ_BASE_LO
SMMU_CMDQ_BASE_HI
SMMU_CMDQ_PROD
SMMU_CMDQ_CONS
SMMU_EVENTQ_BASE_LO
SMMU_EVENTQ_BASE_HI
SMMU_EVENTQ_IRQ_CFG0_LO
SMMU_EVENTQ_IRQ_CFG0_HI
SMMU_EVENTQ_IRQ_CFG1
SMMU_EVENTQ_IRQ_CFG2
SMMU_PRIQ_BASE_LO
SMMU_PRIQ_BASE_HI
SMMU_PRIQ_IRQ_CFG0_LO
SMMU_PRIQ_IRQ_CFG0_HI
SMMU_PRIQ_IRQ_CFG1
SMMU_PRIQ_IRQ_CFG2
SMMU_PIDR4
SMMU_PIDR5
SMMU_PIDR6
SMMU_PIDR7
SMMU_PIDR0
SMMU_PIDR1
SMMU_PIDR2
SMMU_PIDR3
SMMU_CIDR0
SMMU_CIDR1
SMMU_CIDR2
SMMU_CIDR3
SMMU_PMCG_EVTYPER0
SMMU_PMCG_EVTYPER1
SMMU_PMCG_EVTYPER2
SMMU_PMCG_EVTYPER3
SMMU_PMCG_SMR0
SMMU_PMCG_CNTENSET0
SMMU_PMCG_CNTENCLR0
SMMU_PMCG_INTENSET0
SMMU_PMCG_INTENCLR0
SMMU_PMCG_SCR
SMMU_PMCG_CFGR
SMMU_PMCG_CR
SMMU_PMCG_CEID0_LO
SMMU_PMCG_CEID0_HI
SMMU_PMCG_CEID1_LO
SMMU_PMCG_CEID1_HI
SMMU_PMCG_IRQ_CTRL
SMMU_PMCG_IRQ_CTRLACK
SMMU_PMCG_AIDR
SMMU_PMCG_PMAUTHSTATUS
SMMU_PMCG_PMDEVARCH
SMMU_PMCG_PMDEVTYPE
SMMU_PMCG_PIDR4
SMMU_PMCG_PIDR5
SMMU_PMCG_PIDR6
SMMU_PMCG_PIDR7
SMMU_PMCG_PIDR0
SMMU_PMCG_PIDR1
SMMU_PMCG_PIDR2
SMMU_PMCG_PIDR3
SMMU_PMCG_CIDR0
SMMU_PMCG_CIDR1
SMMU_PMCG_CIDR2
SMMU_PMCG_CIDR3
SMMU_S_IDR0
SMMU_S_IDR1
SMMU_S_IDR3
SMMU_S_CR0
SMMU_S_CR0ACK
SMMU_S_CR1
SMMU_S_CR2
SMMU_S_INIT
SMMU_S_GBPA
SMMU_S_IRQ_CTRL
SMMU_S_IRQ_CTRLACK
SMMU_S_GERROR
SMMU_S_GERRORN
SMMU_S_GERROR_IRQ_CFG0_LO
SMMU_S_GERROR_IRQ_CFG0_HI
SMMU_S_GERROR_IRQ_CFG1
SMMU_S_GERROR_IRQ_CFG2
SMMU_S_STRTAB_BASE_LO
SMMU_S_STRTAB_BASE_HI
SMMU_S_STRTAB_BASE_CFG
SMMU_S_CMDQ_BASE_LO
SMMU_S_CMDQ_BASE_HI
SMMU_S_CMDQ_PROD
SMMU_S_CMDQ_CONS
SMMU_S_EVENTQ_BASE_LO
SMMU_S_EVENTQ_BASE_HI
SMMU_S_EVENTQ_PROD
SMMU_S_EVENTQ_CONS
SMMU_S_EVENTQ_IRQ_CFG0_LO
SMMU_S_EVENTQ_IRQ_CFG0_HI
SMMU_S_EVENTQ_IRQ_CFG1
SMMU_S_EVENTQ_IRQ_CFG2
TCU_CTRL
TCU_QOS
TCU_CFG
TCU_STATUS
TCU_SCR
TCU_ERRFR_LO
TCU_ERRFR_HI
TCU_ERRCTLR_LO
TCU_ERRCTLR_HI
TCU_ERRSTATUS_LO
TCU_ERRSTATUS_HI
TCU_ERRGEN_LO
TCU_ERRGEN_HI
TCU_NODE_CTRL0
TCU_NODE_CTRL1
TCU_NODE_CTRL2
TCU_NODE_CTRL3
TCU_NODE_CTRL4
TCU_NODE_CTRL5
TCU_NODE_CTRL6
TCU_NODE_CTRL7
TCU_NODE_CTRL8
TCU_NODE_CTRL9
TCU_NODE_CTRL10
TCU_NODE_CTRL11
TCU_NODE_CTRL12
TCU_NODE_CTRL13
TCU_NODE_CTRL14
TCU_NODE_CTRL15
TCU_NODE_CTRL16
TCU_NODE_CTRL17
TCU_NODE_CTRL18
TCU_NODE_CTRL19
TCU_NODE_CTRL20
TCU_NODE_CTRL21
TCU_NODE_CTRL22
TCU_NODE_CTRL23
TCU_NODE_CTRL24
TCU_NODE_CTRL25
TCU_NODE_CTRL26
TCU_NODE_CTRL27
TCU_NODE_CTRL28
TCU_NODE_CTRL29
TCU_NODE_CTRL30
TCU_NODE_CTRL31
TCU_NODE_CTRL32
TCU_NODE_CTRL33
TCU_NODE_CTRL34
TCU_NODE_CTRL35
TCU_NODE_CTRL36
TCU_NODE_CTRL37
TCU_NODE_CTRL38
TCU_NODE_CTRL39
TCU_NODE_CTRL40
TCU_NODE_CTRL41
TCU_NODE_CTRL42
TCU_NODE_CTRL43
TCU_NODE_CTRL44
TCU_NODE_CTRL45
TCU_NODE_CTRL46
TCU_NODE_CTRL47
TCU_NODE_CTRL48
TCU_NODE_CTRL49
TCU_NODE_CTRL50
TCU_NODE_CTRL51
TCU_NODE_CTRL52
TCU_NODE_CTRL53
TCU_NODE_CTRL54
TCU_NODE_CTRL55
TCU_NODE_CTRL56
TCU_NODE_CTRL57
TCU_NODE_CTRL58
TCU_NODE_CTRL59
TCU_NODE_CTRL60
TCU_NODE_CTRL61
TCU_NODE_STATUS0
TCU_NODE_STATUS1
TCU_NODE_STATUS2
TCU_NODE_STATUS3
TCU_NODE_STATUS4
TCU_NODE_STATUS5
TCU_NODE_STATUS6
TCU_NODE_STATUS7
TCU_NODE_STATUS8
TCU_NODE_STATUS9
TCU_NODE_STATUS10
TCU_NODE_STATUS11
TCU_NODE_STATUS12
TCU_NODE_STATUS13
TCU_NODE_STATUS14
TCU_NODE_STATUS15
TCU_NODE_STATUS16
TCU_NODE_STATUS17
TCU_NODE_STATUS18
TCU_NODE_STATUS19
TCU_NODE_STATUS20
TCU_NODE_STATUS21
TCU_NODE_STATUS22
TCU_NODE_STATUS23
TCU_NODE_STATUS24
TCU_NODE_STATUS25
TCU_NODE_STATUS26
TCU_NODE_STATUS27
TCU_NODE_STATUS28
TCU_NODE_STATUS29
TCU_NODE_STATUS30
TCU_NODE_STATUS31
TCU_NODE_STATUS32
TCU_NODE_STATUS33
TCU_NODE_STATUS34
TCU_NODE_STATUS35
TCU_NODE_STATUS36
TCU_NODE_STATUS37
TCU_NODE_STATUS38
TCU_NODE_STATUS39
TCU_NODE_STATUS40
TCU_NODE_STATUS41
TCU_NODE_STATUS42
TCU_NODE_STATUS43
TCU_NODE_STATUS44
TCU_NODE_STATUS45
TCU_NODE_STATUS46
TCU_NODE_STATUS47
TCU_NODE_STATUS48
TCU_NODE_STATUS49
TCU_NODE_STATUS50
TCU_NODE_STATUS51
TCU_NODE_STATUS52
TCU_NODE_STATUS53
TCU_NODE_STATUS54
TCU_NODE_STATUS55
TCU_NODE_STATUS56
TCU_NODE_STATUS57
TCU_NODE_STATUS58
TCU_NODE_STATUS59
TCU_NODE_STATUS60
TCU_NODE_STATUS61
SMMU_EVENTQ_PROD
SMMU_EVENTQ_CONS
SMMU_PRIQ_PROD
SMMU_PRIQ_CONS
SMMU_PMCG_EVCNTR0
SMMU_PMCG_EVCNTR1
SMMU_PMCG_EVCNTR2
SMMU_PMCG_EVCNTR3
SMMU_PMCG_SVR0
SMMU_PMCG_SVR1
SMMU_PMCG_SVR2
SMMU_PMCG_SVR3
SMMU_PMCG_OVSCLR0
SMMU_PMCG_OVSSET0
SMMU_PMCG_CAPR
MPFE_CSR Address Block Group
MPFE_SCR Address Map
MPFE_SCR Summary
IO96B0_reg
IO96B1_reg
noc_csr
DDR_CCU_dmi1_SCR Address Map
DDR_CCU_dmi1_SCR Summary
enable
enable_set
enable_clear
mpuregion0addr_base
mpuregion0addr_baseext
mpuregion0addr_limit
mpuregion0addr_limitext
mpuregion1addr_base
mpuregion1addr_baseext
mpuregion1addr_limit
mpuregion1addr_limitext
mpuregion2addr_base
mpuregion2addr_baseext
mpuregion2addr_limit
mpuregion2addr_limitext
mpuregion3addr_base
mpuregion3addr_baseext
mpuregion3addr_limit
mpuregion3addr_limitext
mpuregion4addr_base
mpuregion4addr_baseext
mpuregion4addr_limit
mpuregion4addr_limitext
mpuregion5addr_base
mpuregion5addr_baseext
mpuregion5addr_limit
mpuregion5addr_limitext
mpuregion6addr_base
mpuregion6addr_baseext
mpuregion6addr_limit
mpuregion6addr_limitext
mpuregion7addr_base
mpuregion7addr_baseext
mpuregion7addr_limit
mpuregion7addr_limitext
nonmpuregion0addr_base
nonmpuregion0addr_baseext
nonmpuregion0addr_limit
nonmpuregion0addr_limitext
nonmpuregion1addr_base
nonmpuregion1addr_baseext
nonmpuregion1addr_limit
nonmpuregion1addr_limitext
nonmpuregion2addr_base
nonmpuregion2addr_baseext
nonmpuregion2addr_limit
nonmpuregion2addr_limitext
nonmpuregion3addr_base
nonmpuregion3addr_baseext
nonmpuregion3addr_limit
nonmpuregion3addr_limitext
nonmpuregion4addr_base
nonmpuregion4addr_baseext
nonmpuregion4addr_limit
nonmpuregion4addr_limitext
nonmpuregion5addr_base
nonmpuregion5addr_baseext
nonmpuregion5addr_limit
nonmpuregion5addr_limitext
nonmpuregion6addr_base
nonmpuregion6addr_baseext
nonmpuregion6addr_limit
nonmpuregion6addr_limitext
nonmpuregion7addr_base
nonmpuregion7addr_baseext
nonmpuregion7addr_limit
nonmpuregion7addr_limitext
DDR_CCU_dmi0_SCR Address Map
DDR_CCU_dmi0_SCR Summary
enable
enable_set
enable_clear
mpuregion0addr_base
mpuregion0addr_baseext
mpuregion0addr_limit
mpuregion0addr_limitext
mpuregion1addr_base
mpuregion1addr_baseext
mpuregion1addr_limit
mpuregion1addr_limitext
mpuregion2addr_base
mpuregion2addr_baseext
mpuregion2addr_limit
mpuregion2addr_limitext
mpuregion3addr_base
mpuregion3addr_baseext
mpuregion3addr_limit
mpuregion3addr_limitext
mpuregion4addr_base
mpuregion4addr_baseext
mpuregion4addr_limit
mpuregion4addr_limitext
mpuregion5addr_base
mpuregion5addr_baseext
mpuregion5addr_limit
mpuregion5addr_limitext
mpuregion6addr_base
mpuregion6addr_baseext
mpuregion6addr_limit
mpuregion6addr_limitext
mpuregion7addr_base
mpuregion7addr_baseext
mpuregion7addr_limit
mpuregion7addr_limitext
nonmpuregion0addr_base
nonmpuregion0addr_baseext
nonmpuregion0addr_limit
nonmpuregion0addr_limitext
nonmpuregion1addr_base
nonmpuregion1addr_baseext
nonmpuregion1addr_limit
nonmpuregion1addr_limitext
nonmpuregion2addr_base
nonmpuregion2addr_baseext
nonmpuregion2addr_limit
nonmpuregion2addr_limitext
nonmpuregion3addr_base
nonmpuregion3addr_baseext
nonmpuregion3addr_limit
nonmpuregion3addr_limitext
nonmpuregion4addr_base
nonmpuregion4addr_baseext
nonmpuregion4addr_limit
nonmpuregion4addr_limitext
nonmpuregion5addr_base
nonmpuregion5addr_baseext
nonmpuregion5addr_limit
nonmpuregion5addr_limitext
nonmpuregion6addr_base
nonmpuregion6addr_baseext
nonmpuregion6addr_limit
nonmpuregion6addr_limitext
nonmpuregion7addr_base
nonmpuregion7addr_baseext
nonmpuregion7addr_limit
nonmpuregion7addr_limitext
mpfe_read_probe Address Map
mpfe_read_probe Summary
mpfe_read_probe_main_Probe_Id_CoreId
mpfe_read_probe_main_Probe_Id_RevisionId
mpfe_read_probe_main_Probe_MainCtl
mpfe_read_probe_main_Probe_CfgCtl
mpfe_read_probe_main_Probe_TracePortSel
mpfe_read_probe_main_Probe_FilterLut
mpfe_read_probe_main_Probe_TraceAlarmEn
mpfe_read_probe_main_Probe_TraceAlarmStatus
mpfe_read_probe_main_Probe_TraceAlarmClr
mpfe_read_probe_main_Probe_StatPeriod
mpfe_read_probe_main_Probe_StatGo
mpfe_read_probe_main_Probe_StatAlarmMin
mpfe_read_probe_main_Probe_StatAlarmMax
mpfe_read_probe_main_Probe_StatAlarmStatus
mpfe_read_probe_main_Probe_StatAlarmClr
mpfe_read_probe_main_Probe_StatAlarmEn
mpfe_read_probe_main_Probe_Filters_0_RouteIdBase
mpfe_read_probe_main_Probe_Filters_0_RouteIdMask
mpfe_read_probe_main_Probe_Filters_0_AddrBase_Low
mpfe_read_probe_main_Probe_Filters_0_AddrBase_High
mpfe_read_probe_main_Probe_Filters_0_WindowSize
mpfe_read_probe_main_Probe_Filters_0_SecurityBase
mpfe_read_probe_main_Probe_Filters_0_SecurityMask
mpfe_read_probe_main_Probe_Filters_0_Opcode
mpfe_read_probe_main_Probe_Filters_0_Status
mpfe_read_probe_main_Probe_Filters_0_Length
mpfe_read_probe_main_Probe_Filters_0_Urgency
mpfe_read_probe_main_Probe_Filters_0_UserBase
mpfe_read_probe_main_Probe_Filters_0_UserMask
mpfe_read_probe_main_Probe_Filters_0_UserBaseHigh
mpfe_read_probe_main_Probe_Filters_0_UserMaskHigh
mpfe_read_probe_main_Probe_Filters_1_RouteIdBase
mpfe_read_probe_main_Probe_Filters_1_RouteIdMask
mpfe_read_probe_main_Probe_Filters_1_AddrBase_Low
mpfe_read_probe_main_Probe_Filters_1_AddrBase_High
mpfe_read_probe_main_Probe_Filters_1_WindowSize
mpfe_read_probe_main_Probe_Filters_1_SecurityBase
mpfe_read_probe_main_Probe_Filters_1_SecurityMask
mpfe_read_probe_main_Probe_Filters_1_Opcode
mpfe_read_probe_main_Probe_Filters_1_Status
mpfe_read_probe_main_Probe_Filters_1_Length
mpfe_read_probe_main_Probe_Filters_1_Urgency
mpfe_read_probe_main_Probe_Filters_1_UserBase
mpfe_read_probe_main_Probe_Filters_1_UserMask
mpfe_read_probe_main_Probe_Filters_1_UserBaseHigh
mpfe_read_probe_main_Probe_Filters_1_UserMaskHigh
mpfe_read_probe_main_Probe_Filters_2_RouteIdBase
mpfe_read_probe_main_Probe_Filters_2_RouteIdMask
mpfe_read_probe_main_Probe_Filters_2_AddrBase_Low
mpfe_read_probe_main_Probe_Filters_2_AddrBase_High
mpfe_read_probe_main_Probe_Filters_2_WindowSize
mpfe_read_probe_main_Probe_Filters_2_SecurityBase
mpfe_read_probe_main_Probe_Filters_2_SecurityMask
mpfe_read_probe_main_Probe_Filters_2_Opcode
mpfe_read_probe_main_Probe_Filters_2_Status
mpfe_read_probe_main_Probe_Filters_2_Length
mpfe_read_probe_main_Probe_Filters_2_Urgency
mpfe_read_probe_main_Probe_Filters_2_UserBase
mpfe_read_probe_main_Probe_Filters_2_UserMask
mpfe_read_probe_main_Probe_Filters_2_UserBaseHigh
mpfe_read_probe_main_Probe_Filters_2_UserMaskHigh
mpfe_read_probe_main_Probe_Filters_3_RouteIdBase
mpfe_read_probe_main_Probe_Filters_3_RouteIdMask
mpfe_read_probe_main_Probe_Filters_3_AddrBase_Low
mpfe_read_probe_main_Probe_Filters_3_AddrBase_High
mpfe_read_probe_main_Probe_Filters_3_WindowSize
mpfe_read_probe_main_Probe_Filters_3_SecurityBase
mpfe_read_probe_main_Probe_Filters_3_SecurityMask
mpfe_read_probe_main_Probe_Filters_3_Opcode
mpfe_read_probe_main_Probe_Filters_3_Status
mpfe_read_probe_main_Probe_Filters_3_Length
mpfe_read_probe_main_Probe_Filters_3_Urgency
mpfe_read_probe_main_Probe_Filters_3_UserBase
mpfe_read_probe_main_Probe_Filters_3_UserMask
mpfe_read_probe_main_Probe_Filters_3_UserBaseHigh
mpfe_read_probe_main_Probe_Filters_3_UserMaskHigh
mpfe_read_probe_main_Probe_Counters_0_PortSel
mpfe_read_probe_main_Probe_Counters_0_Src
mpfe_read_probe_main_Probe_Counters_0_AlarmMode
mpfe_read_probe_main_Probe_Counters_0_Val
mpfe_read_probe_main_Probe_Counters_1_PortSel
mpfe_read_probe_main_Probe_Counters_1_Src
mpfe_read_probe_main_Probe_Counters_1_AlarmMode
mpfe_read_probe_main_Probe_Counters_1_Val
mpfe_read_probe_main_Probe_Counters_2_PortSel
mpfe_read_probe_main_Probe_Counters_2_Src
mpfe_read_probe_main_Probe_Counters_2_AlarmMode
mpfe_read_probe_main_Probe_Counters_2_Val
mpfe_read_probe_main_Probe_Counters_3_PortSel
mpfe_read_probe_main_Probe_Counters_3_Src
mpfe_read_probe_main_Probe_Counters_3_AlarmMode
mpfe_read_probe_main_Probe_Counters_3_Val
mpfe_read_probe_main_Probe_Counters_4_PortSel
mpfe_read_probe_main_Probe_Counters_4_Src
mpfe_read_probe_main_Probe_Counters_4_AlarmMode
mpfe_read_probe_main_Probe_Counters_4_Val
mpfe_read_probe_main_Probe_Counters_5_PortSel
mpfe_read_probe_main_Probe_Counters_5_Src
mpfe_read_probe_main_Probe_Counters_5_AlarmMode
mpfe_read_probe_main_Probe_Counters_5_Val
mpfe_read_probe_main_Probe_Counters_6_PortSel
mpfe_read_probe_main_Probe_Counters_6_Src
mpfe_read_probe_main_Probe_Counters_6_AlarmMode
mpfe_read_probe_main_Probe_Counters_6_Val
mpfe_read_probe_main_Probe_Counters_7_PortSel
mpfe_read_probe_main_Probe_Counters_7_Src
mpfe_read_probe_main_Probe_Counters_7_AlarmMode
mpfe_read_probe_main_Probe_Counters_7_Val
mpfe_read_probe_main_Probe_Counters_8_PortSel
mpfe_read_probe_main_Probe_Counters_8_Src
mpfe_read_probe_main_Probe_Counters_8_AlarmMode
mpfe_read_probe_main_Probe_Counters_8_Val
mpfe_read_probe_main_Probe_Counters_9_PortSel
mpfe_read_probe_main_Probe_Counters_9_Src
mpfe_read_probe_main_Probe_Counters_9_AlarmMode
mpfe_read_probe_main_Probe_Counters_9_Val
mpfe_read_probe_main_Probe_Counters_10_PortSel
mpfe_read_probe_main_Probe_Counters_10_Src
mpfe_read_probe_main_Probe_Counters_10_AlarmMode
mpfe_read_probe_main_Probe_Counters_10_Val
mpfe_read_probe_main_Probe_Counters_11_PortSel
mpfe_read_probe_main_Probe_Counters_11_Src
mpfe_read_probe_main_Probe_Counters_11_AlarmMode
mpfe_read_probe_main_Probe_Counters_11_Val
mpfe_read_probe_main_Probe_Counters_12_PortSel
mpfe_read_probe_main_Probe_Counters_12_Src
mpfe_read_probe_main_Probe_Counters_12_AlarmMode
mpfe_read_probe_main_Probe_Counters_12_Val
mpfe_read_probe_main_Probe_Counters_13_PortSel
mpfe_read_probe_main_Probe_Counters_13_Src
mpfe_read_probe_main_Probe_Counters_13_AlarmMode
mpfe_read_probe_main_Probe_Counters_13_Val
mpfe_read_probe_main_Probe_Counters_14_PortSel
mpfe_read_probe_main_Probe_Counters_14_Src
mpfe_read_probe_main_Probe_Counters_14_AlarmMode
mpfe_read_probe_main_Probe_Counters_14_Val
mpfe_read_probe_main_Probe_Counters_15_PortSel
mpfe_read_probe_main_Probe_Counters_15_Src
mpfe_read_probe_main_Probe_Counters_15_AlarmMode
mpfe_read_probe_main_Probe_Counters_15_Val
mpfe_write_probe Address Map
mpfe_write_probe Summary
mpfe_write_probe_main_Probe_Id_CoreId
mpfe_write_probe_main_Probe_Id_RevisionId
mpfe_write_probe_main_Probe_MainCtl
mpfe_write_probe_main_Probe_CfgCtl
mpfe_write_probe_main_Probe_TracePortSel
mpfe_write_probe_main_Probe_FilterLut
mpfe_write_probe_main_Probe_TraceAlarmEn
mpfe_write_probe_main_Probe_TraceAlarmStatus
mpfe_write_probe_main_Probe_TraceAlarmClr
mpfe_write_probe_main_Probe_StatPeriod
mpfe_write_probe_main_Probe_StatGo
mpfe_write_probe_main_Probe_StatAlarmMin
mpfe_write_probe_main_Probe_StatAlarmMax
mpfe_write_probe_main_Probe_StatAlarmStatus
mpfe_write_probe_main_Probe_StatAlarmClr
mpfe_write_probe_main_Probe_StatAlarmEn
mpfe_write_probe_main_Probe_Filters_0_RouteIdBase
mpfe_write_probe_main_Probe_Filters_0_RouteIdMask
mpfe_write_probe_main_Probe_Filters_0_AddrBase_Low
mpfe_write_probe_main_Probe_Filters_0_AddrBase_High
mpfe_write_probe_main_Probe_Filters_0_WindowSize
mpfe_write_probe_main_Probe_Filters_0_SecurityBase
mpfe_write_probe_main_Probe_Filters_0_SecurityMask
mpfe_write_probe_main_Probe_Filters_0_Opcode
mpfe_write_probe_main_Probe_Filters_0_Status
mpfe_write_probe_main_Probe_Filters_0_Length
mpfe_write_probe_main_Probe_Filters_0_Urgency
mpfe_write_probe_main_Probe_Filters_0_UserBase
mpfe_write_probe_main_Probe_Filters_0_UserMask
mpfe_write_probe_main_Probe_Filters_0_UserBaseHigh
mpfe_write_probe_main_Probe_Filters_0_UserMaskHigh
mpfe_write_probe_main_Probe_Filters_1_RouteIdBase
mpfe_write_probe_main_Probe_Filters_1_RouteIdMask
mpfe_write_probe_main_Probe_Filters_1_AddrBase_Low
mpfe_write_probe_main_Probe_Filters_1_AddrBase_High
mpfe_write_probe_main_Probe_Filters_1_WindowSize
mpfe_write_probe_main_Probe_Filters_1_SecurityBase
mpfe_write_probe_main_Probe_Filters_1_SecurityMask
mpfe_write_probe_main_Probe_Filters_1_Opcode
mpfe_write_probe_main_Probe_Filters_1_Status
mpfe_write_probe_main_Probe_Filters_1_Length
mpfe_write_probe_main_Probe_Filters_1_Urgency
mpfe_write_probe_main_Probe_Filters_1_UserBase
mpfe_write_probe_main_Probe_Filters_1_UserMask
mpfe_write_probe_main_Probe_Filters_1_UserBaseHigh
mpfe_write_probe_main_Probe_Filters_1_UserMaskHigh
mpfe_write_probe_main_Probe_Filters_2_RouteIdBase
mpfe_write_probe_main_Probe_Filters_2_RouteIdMask
mpfe_write_probe_main_Probe_Filters_2_AddrBase_Low
mpfe_write_probe_main_Probe_Filters_2_AddrBase_High
mpfe_write_probe_main_Probe_Filters_2_WindowSize
mpfe_write_probe_main_Probe_Filters_2_SecurityBase
mpfe_write_probe_main_Probe_Filters_2_SecurityMask
mpfe_write_probe_main_Probe_Filters_2_Opcode
mpfe_write_probe_main_Probe_Filters_2_Status
mpfe_write_probe_main_Probe_Filters_2_Length
mpfe_write_probe_main_Probe_Filters_2_Urgency
mpfe_write_probe_main_Probe_Filters_2_UserBase
mpfe_write_probe_main_Probe_Filters_2_UserMask
mpfe_write_probe_main_Probe_Filters_2_UserBaseHigh
mpfe_write_probe_main_Probe_Filters_2_UserMaskHigh
mpfe_write_probe_main_Probe_Filters_3_RouteIdBase
mpfe_write_probe_main_Probe_Filters_3_RouteIdMask
mpfe_write_probe_main_Probe_Filters_3_AddrBase_Low
mpfe_write_probe_main_Probe_Filters_3_AddrBase_High
mpfe_write_probe_main_Probe_Filters_3_WindowSize
mpfe_write_probe_main_Probe_Filters_3_SecurityBase
mpfe_write_probe_main_Probe_Filters_3_SecurityMask
mpfe_write_probe_main_Probe_Filters_3_Opcode
mpfe_write_probe_main_Probe_Filters_3_Status
mpfe_write_probe_main_Probe_Filters_3_Length
mpfe_write_probe_main_Probe_Filters_3_Urgency
mpfe_write_probe_main_Probe_Filters_3_UserBase
mpfe_write_probe_main_Probe_Filters_3_UserMask
mpfe_write_probe_main_Probe_Filters_3_UserBaseHigh
mpfe_write_probe_main_Probe_Filters_3_UserMaskHigh
mpfe_write_probe_main_Probe_Counters_0_PortSel
mpfe_write_probe_main_Probe_Counters_0_Src
mpfe_write_probe_main_Probe_Counters_0_AlarmMode
mpfe_write_probe_main_Probe_Counters_0_Val
mpfe_write_probe_main_Probe_Counters_1_PortSel
mpfe_write_probe_main_Probe_Counters_1_Src
mpfe_write_probe_main_Probe_Counters_1_AlarmMode
mpfe_write_probe_main_Probe_Counters_1_Val
mpfe_write_probe_main_Probe_Counters_2_PortSel
mpfe_write_probe_main_Probe_Counters_2_Src
mpfe_write_probe_main_Probe_Counters_2_AlarmMode
mpfe_write_probe_main_Probe_Counters_2_Val
mpfe_write_probe_main_Probe_Counters_3_PortSel
mpfe_write_probe_main_Probe_Counters_3_Src
mpfe_write_probe_main_Probe_Counters_3_AlarmMode
mpfe_write_probe_main_Probe_Counters_3_Val
mpfe_write_probe_main_Probe_Counters_4_PortSel
mpfe_write_probe_main_Probe_Counters_4_Src
mpfe_write_probe_main_Probe_Counters_4_AlarmMode
mpfe_write_probe_main_Probe_Counters_4_Val
mpfe_write_probe_main_Probe_Counters_5_PortSel
mpfe_write_probe_main_Probe_Counters_5_Src
mpfe_write_probe_main_Probe_Counters_5_AlarmMode
mpfe_write_probe_main_Probe_Counters_5_Val
mpfe_write_probe_main_Probe_Counters_6_PortSel
mpfe_write_probe_main_Probe_Counters_6_Src
mpfe_write_probe_main_Probe_Counters_6_AlarmMode
mpfe_write_probe_main_Probe_Counters_6_Val
mpfe_write_probe_main_Probe_Counters_7_PortSel
mpfe_write_probe_main_Probe_Counters_7_Src
mpfe_write_probe_main_Probe_Counters_7_AlarmMode
mpfe_write_probe_main_Probe_Counters_7_Val
mpfe_write_probe_main_Probe_Counters_8_PortSel
mpfe_write_probe_main_Probe_Counters_8_Src
mpfe_write_probe_main_Probe_Counters_8_AlarmMode
mpfe_write_probe_main_Probe_Counters_8_Val
mpfe_write_probe_main_Probe_Counters_9_PortSel
mpfe_write_probe_main_Probe_Counters_9_Src
mpfe_write_probe_main_Probe_Counters_9_AlarmMode
mpfe_write_probe_main_Probe_Counters_9_Val
mpfe_write_probe_main_Probe_Counters_10_PortSel
mpfe_write_probe_main_Probe_Counters_10_Src
mpfe_write_probe_main_Probe_Counters_10_AlarmMode
mpfe_write_probe_main_Probe_Counters_10_Val
mpfe_write_probe_main_Probe_Counters_11_PortSel
mpfe_write_probe_main_Probe_Counters_11_Src
mpfe_write_probe_main_Probe_Counters_11_AlarmMode
mpfe_write_probe_main_Probe_Counters_11_Val
mpfe_write_probe_main_Probe_Counters_12_PortSel
mpfe_write_probe_main_Probe_Counters_12_Src
mpfe_write_probe_main_Probe_Counters_12_AlarmMode
mpfe_write_probe_main_Probe_Counters_12_Val
mpfe_write_probe_main_Probe_Counters_13_PortSel
mpfe_write_probe_main_Probe_Counters_13_Src
mpfe_write_probe_main_Probe_Counters_13_AlarmMode
mpfe_write_probe_main_Probe_Counters_13_Val
mpfe_write_probe_main_Probe_Counters_14_PortSel
mpfe_write_probe_main_Probe_Counters_14_Src
mpfe_write_probe_main_Probe_Counters_14_AlarmMode
mpfe_write_probe_main_Probe_Counters_14_Val
mpfe_write_probe_main_Probe_Counters_15_PortSel
mpfe_write_probe_main_Probe_Counters_15_Src
mpfe_write_probe_main_Probe_Counters_15_AlarmMode
mpfe_write_probe_main_Probe_Counters_15_Val
ccu_dmi0_firewall Address Map
ccu_dmi1_firewall Address Map
tbu2noc_firewall Address Map
mpfe_csr_firewall Address Map
mpfe_read_probe_TransactionStatProfiler Address Map
mpfe_read_probe_TransactionStatProfiler Summary
mpfe_read_probe_main_TransactionStatProfiler_Id_CoreId
mpfe_read_probe_main_TransactionStatProfiler_Id_RevisionId
mpfe_read_probe_main_TransactionStatProfiler_En
mpfe_read_probe_main_TransactionStatProfiler_Mode
mpfe_read_probe_main_TransactionStatProfiler_ObservedSel_0
mpfe_read_probe_main_TransactionStatProfiler_ObservedSel_1
mpfe_read_probe_main_TransactionStatProfiler_ObservedSel_2
mpfe_read_probe_main_TransactionStatProfiler_NTenureLines_0
mpfe_read_probe_main_TransactionStatProfiler_NTenureLines_1
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_0_0
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_0_1
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_0_2
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_0_3
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_0_4
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_0_5
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_0_6
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_0_7
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_0_8
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_0_9
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_0_10
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_0_11
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_0_12
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_0_13
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_0_14
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_1_0
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_1_1
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_1_2
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_1_3
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_1_4
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_1_5
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_1_6
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_1_7
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_1_8
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_1_9
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_1_10
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_1_11
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_1_12
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_1_13
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_1_14
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_2_0
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_2_1
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_2_2
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_2_3
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_2_4
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_2_5
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_2_6
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_2_7
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_2_8
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_2_9
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_2_10
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_2_11
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_2_12
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_2_13
mpfe_read_probe_main_TransactionStatProfiler_Thresholds_2_14
mpfe_read_probe_main_TransactionStatProfiler_OverflowStatus
mpfe_read_probe_main_TransactionStatProfiler_OverflowReset
mpfe_read_probe_main_TransactionStatProfiler_PendingEventMode
mpfe_read_probe_main_TransactionStatProfiler_PreScaler
fpga2sdram_manager Address Map
fpga2sdram_manager Summary
fpga2sdram_manager_main_SidebandManager_Id_CoreId
fpga2sdram_manager_main_SidebandManager_Id_RevisionId
fpga2sdram_manager_main_SidebandManager_FaultEn
fpga2sdram_manager_main_SidebandManager_FaultStatus
fpga2sdram_manager_main_SidebandManager_FlagInEn0
fpga2sdram_manager_main_SidebandManager_FlagInStatus0
fpga2sdram_manager_main_SidebandManager_FlagOutSet0
fpga2sdram_manager_main_SidebandManager_FlagOutClr0
fpga2sdram_manager_main_SidebandManager_FlagOutStatus0
cs_obs_at_main_AtbEndPoint Address Map
cs_obs_at_main_AtbEndPoint Summary
cs_obs_at_main_AtbEndPoint_Id_CoreId
cs_obs_at_main_AtbEndPoint_Id_RevisionId
cs_obs_at_main_AtbEndPoint_AtbId
cs_obs_at_main_AtbEndPoint_AtbEn
cs_obs_at_main_ErrorLogger_0 Address Map
cs_obs_at_main_ErrorLogger_0 Summary
cs_obs_at_main_ErrorLogger_0_Id_CoreId
cs_obs_at_main_ErrorLogger_0_Id_RevisionId
cs_obs_at_main_ErrorLogger_0_FaultEn
cs_obs_at_main_ErrorLogger_0_ErrVld
cs_obs_at_main_ErrorLogger_0_ErrClr
cs_obs_at_main_ErrorLogger_0_ErrLog0
cs_obs_at_main_ErrorLogger_0_ErrLog1
cs_obs_at_main_ErrorLogger_0_ErrLog3
cs_obs_at_main_ErrorLogger_0_ErrLog4
cs_obs_at_main_ErrorLogger_0_ErrLog5
cs_obs_at_main_ErrorLogger_0_ErrLog6
cs_obs_at_main_ErrorLogger_0_ErrLog7
cs_obs_at_main_ErrorLogger_0_StallEn
cs_obs_at_main_ErrorLogger_1 Address Map
cs_obs_at_main_ErrorLogger_1 Summary
cs_obs_at_main_ErrorLogger_1_Id_CoreId
cs_obs_at_main_ErrorLogger_1_Id_RevisionId
cs_obs_at_main_ErrorLogger_1_FaultEn
cs_obs_at_main_ErrorLogger_1_ErrVld
cs_obs_at_main_ErrorLogger_1_ErrClr
cs_obs_at_main_ErrorLogger_1_ErrLog0
cs_obs_at_main_ErrorLogger_1_ErrLog1
cs_obs_at_main_ErrorLogger_1_ErrLog3
cs_obs_at_main_ErrorLogger_1_ErrLog4
cs_obs_at_main_ErrorLogger_1_ErrLog5
cs_obs_at_main_ErrorLogger_1_ErrLog6
cs_obs_at_main_ErrorLogger_1_ErrLog7
cs_obs_at_main_ErrorLogger_1_StallEn
ccu_dmi0_I_main_QosGenerator Address Map
ccu_dmi0_I_main_QosGenerator Summary
ccu_dmi0_I_main_QosGenerator_Id_CoreId
ccu_dmi0_I_main_QosGenerator_Id_RevisionId
ccu_dmi0_I_main_QosGenerator_Priority
ccu_dmi0_I_main_QosGenerator_Mode
ccu_dmi0_I_main_QosGenerator_Bandwidth
ccu_dmi0_I_main_QosGenerator_Saturation
ccu_dmi0_I_main_QosGenerator_ExtControl
ccu_dmi1_I_main_QosGenerator Address Map
ccu_dmi1_I_main_QosGenerator Summary
ccu_dmi1_I_main_QosGenerator_Id_CoreId
ccu_dmi1_I_main_QosGenerator_Id_RevisionId
ccu_dmi1_I_main_QosGenerator_Priority
ccu_dmi1_I_main_QosGenerator_Mode
ccu_dmi1_I_main_QosGenerator_Bandwidth
ccu_dmi1_I_main_QosGenerator_Saturation
ccu_dmi1_I_main_QosGenerator_ExtControl
tbu2noc_I_main_QosGenerator Address Map
tbu2noc_I_main_QosGenerator Summary
tbu2noc_I_main_QosGenerator_Id_CoreId
tbu2noc_I_main_QosGenerator_Id_RevisionId
tbu2noc_I_main_QosGenerator_Priority
tbu2noc_I_main_QosGenerator_Mode
tbu2noc_I_main_QosGenerator_Bandwidth
tbu2noc_I_main_QosGenerator_Saturation
tbu2noc_I_main_QosGenerator_ExtControl
cs_obs_at_main_STPv2Converter Address Map
cs_obs_at_main_STPv2Converter Summary
cs_obs_at_main_STPv2Converter_Id_CoreId
cs_obs_at_main_STPv2Converter_Id_RevisionId
cs_obs_at_main_STPv2Converter_AsyncPeriod
cs_obs_at_main_STPv2Converter_STPV2En
ccu_dmi0_I_main_TransactionStatFilter Address Map
ccu_dmi0_I_main_TransactionStatFilter Summary
ccu_dmi0_I_main_TransactionStatFilter_Id_CoreId
ccu_dmi0_I_main_TransactionStatFilter_Id_RevisionId
ccu_dmi0_I_main_TransactionStatFilter_Mode
ccu_dmi0_I_main_TransactionStatFilter_AddrBase_Low
ccu_dmi0_I_main_TransactionStatFilter_AddrBase_High
ccu_dmi0_I_main_TransactionStatFilter_AddrWindowSize
ccu_dmi0_I_main_TransactionStatFilter_Opcode
ccu_dmi0_I_main_TransactionStatFilter_UserBase
ccu_dmi0_I_main_TransactionStatFilter_UserMask
ccu_dmi0_I_main_TransactionStatFilter_SecurityBase
ccu_dmi0_I_main_TransactionStatFilter_SecurityMask
ccu_dmi0_I_main_TransactionStatFilter_UserBaseHigh
ccu_dmi0_I_main_TransactionStatFilter_UserMaskHigh
ccu_dmi1_I_main_TransactionStatFilter Address Map
ccu_dmi1_I_main_TransactionStatFilter Summary
ccu_dmi1_I_main_TransactionStatFilter_Id_CoreId
ccu_dmi1_I_main_TransactionStatFilter_Id_RevisionId
ccu_dmi1_I_main_TransactionStatFilter_Mode
ccu_dmi1_I_main_TransactionStatFilter_AddrBase_Low
ccu_dmi1_I_main_TransactionStatFilter_AddrBase_High
ccu_dmi1_I_main_TransactionStatFilter_AddrWindowSize
ccu_dmi1_I_main_TransactionStatFilter_Opcode
ccu_dmi1_I_main_TransactionStatFilter_UserBase
ccu_dmi1_I_main_TransactionStatFilter_UserMask
ccu_dmi1_I_main_TransactionStatFilter_SecurityBase
ccu_dmi1_I_main_TransactionStatFilter_SecurityMask
ccu_dmi1_I_main_TransactionStatFilter_UserBaseHigh
ccu_dmi1_I_main_TransactionStatFilter_UserMaskHigh
tbu2noc_I_main_TransactionStatFilter Address Map
tbu2noc_I_main_TransactionStatFilter Summary
tbu2noc_I_main_TransactionStatFilter_Id_CoreId
tbu2noc_I_main_TransactionStatFilter_Id_RevisionId
tbu2noc_I_main_TransactionStatFilter_Mode
tbu2noc_I_main_TransactionStatFilter_AddrBase_Low
tbu2noc_I_main_TransactionStatFilter_AddrBase_High
tbu2noc_I_main_TransactionStatFilter_AddrWindowSize
tbu2noc_I_main_TransactionStatFilter_Opcode
tbu2noc_I_main_TransactionStatFilter_UserBase
tbu2noc_I_main_TransactionStatFilter_UserMask
tbu2noc_I_main_TransactionStatFilter_SecurityBase
tbu2noc_I_main_TransactionStatFilter_SecurityMask
tbu2noc_I_main_TransactionStatFilter_UserBaseHigh
tbu2noc_I_main_TransactionStatFilter_UserMaskHigh
DDR_SCR Address Map
DDR_SCR Summary
enable
enable_set
enable_clear
region0addr_base
region0addr_baseext
region0addr_limit
region0addr_limitext
region1addr_base
region1addr_baseext
region1addr_limit
region1addr_limitext
region2addr_base
region2addr_baseext
region2addr_limit
region2addr_limitext
region3addr_base
region3addr_baseext
region3addr_limit
region3addr_limitext
region4addr_base
region4addr_baseext
region4addr_limit
region4addr_limitext
region5addr_base
region5addr_baseext
region5addr_limit
region5addr_limitext
region6addr_base
region6addr_baseext
region6addr_limit
region6addr_limitext
region7addr_base
region7addr_baseext
region7addr_limit
region7addr_limitext
CCU Address Block Group
CCU_DSU Address Map
CCU_DSU Summary
CAIUIDR
CAIUFUIDR
CAIUTCR
CAIUTAR
CAIUUEDR
CAIUUEIR
CAIUUESR
CAIUUELR0
CAIUUELR1
CAIUUESAR
CAIUCRTR
CAIUTOCR
CAIUQOSCR
CAIUQOSSR
NRSBAR
NRSBHR
NRSBLR
CAIUBRAR
CAIUBRBLR
CAIUBRBHR
CAIUAMIGR
CAIUMIFSR
CAIUGPRAR0
CAIUGPRBLR0
CAIUGPRBHR0
CAIUGPRAR1
CAIUGPRBLR1
CAIUGPRBHR1
CAIUGPRAR2
CAIUGPRBLR2
CAIUGPRBHR2
CAIUGPRAR3
CAIUGPRBLR3
CAIUGPRBHR3
CAIUGPRAR4
CAIUGPRBLR4
CAIUGPRBHR4
CAIUGPRAR5
CAIUGPRBLR5
CAIUGPRBHR5
CAIUGPRAR6
CAIUGPRBLR6
CAIUGPRBHR6
CAIUGPRAR7
CAIUGPRBLR7
CAIUGPRBHR7
CAIUGPRAR8
CAIUGPRBLR8
CAIUGPRBHR8
CAIUGPRAR9
CAIUGPRBLR9
CAIUGPRBHR9
CAIUGPRAR10
CAIUGPRBLR10
CAIUGPRBHR10
CAIUGPRAR11
CAIUGPRBLR11
CAIUGPRBHR11
CAIUCCTRLR
CAIUTCTRLR0
CAIUTBALR0
CAIUTBAHR0
CAIUTOPCR00
CAIUTOPCR10
CAIUTUBR0
CAIUTUBMR0
CAIUCNTCR0
CAIUCNTVR0
CAIUCNTSR0
CAIUCNTCR1
CAIUCNTVR1
CAIUCNTSR1
CAIUCNTCR2
CAIUCNTVR2
CAIUCNTSR2
CAIUCNTCR3
CAIUCNTVR3
CAIUCNTSR3
CAIUNRSAR
CAIUUEVIR
CAIUINFOR
FPGA2SOC Address Map
FPGA2SOC Summary
XAIUIDR
XAIUFUIDR
XAIUTCR
XAIUTAR
XAIUUEDR
XAIUUEIR
XAIUUESR
XAIUUELR0
XAIUUELR1
XAIUUESAR
XAIUCECR
XAIUCESR
XAIUCELR0
XAIUCELR1
XAIUCESAR
XAIUCRTR
XAIUTOCR
XAIUQOSCR
XAIUQOSSR
XAIUNRSBAR
XAIUNRSBHR
XAIUNRSBLR
XAIUBRAR
XAIUBRBLR
XAIUBRBHR
XAIUAMIGR
XAIUMIFSR
XAIUGPRAR0
XAIUGPRBLR0
XAIUGPRBHR0
XAIUGPRAR1
XAIUGPRBLR1
XAIUGPRBHR1
XAIUGPRAR2
XAIUGPRBLR2
XAIUGPRBHR2
XAIUGPRAR3
XAIUGPRBLR3
XAIUGPRBHR3
XAIUGPRAR4
XAIUGPRBLR4
XAIUGPRBHR4
XAIUGPRAR5
XAIUGPRBLR5
XAIUGPRBHR5
XAIUGPRAR6
XAIUGPRBLR6
XAIUGPRBHR6
XAIUGPRAR7
XAIUGPRBLR7
XAIUGPRBHR7
XAIUGPRAR8
XAIUGPRBLR8
XAIUGPRBHR8
XAIUGPRAR9
XAIUGPRBLR9
XAIUGPRBHR9
XAIUGPRAR10
XAIUGPRBLR10
XAIUGPRBHR10
XAIUGPRAR11
XAIUGPRBLR11
XAIUGPRBHR11
XAIUTBALR0
XAIUTBAHR0
XAIUTOPCR00
XAIUTOPCR10
XAIUTUBR0
XAIUTUBMR0
XAIUCCTRLR
XAIUTCTRLR0
XAIUEDR0
XAIUEDR1
XAIUEDR2
XAIUEDR3
XAIUEDR4
XAIUEDR5
XAIUEDR6
XAIUEDR7
XAIUCNTCR0
XAIUCNTVR0
XAIUCNTSR0
XAIUCNTCR1
XAIUCNTVR1
XAIUCNTSR1
XAIUCNTCR2
XAIUCNTVR2
XAIUCNTSR2
XAIUCNTCR3
XAIUCNTVR3
XAIUCNTSR3
XAIUNRSAR
XAIUENGIDR
XAIUINFOR
GIC_M Address Map
GIC_M Summary
XAIUIDR
XAIUFUIDR
XAIUTCR
XAIUTAR
XAIUUEDR
XAIUUEIR
XAIUUESR
XAIUUELR0
XAIUUELR1
XAIUUESAR
XAIUCECR
XAIUCESR
XAIUCELR0
XAIUCELR1
XAIUCESAR
XAIUCRTR
XAIUTOCR
XAIUQOSCR
XAIUQOSSR
XAIUNRSBAR
XAIUNRSBHR
XAIUNRSBLR
XAIUBRAR
XAIUBRBLR
XAIUBRBHR
XAIUAMIGR
XAIUMIFSR
XAIUGPRAR0
XAIUGPRBLR0
XAIUGPRBHR0
XAIUGPRAR1
XAIUGPRBLR1
XAIUGPRBHR1
XAIUGPRAR2
XAIUGPRBLR2
XAIUGPRBHR2
XAIUGPRAR3
XAIUGPRBLR3
XAIUGPRBHR3
XAIUGPRAR4
XAIUGPRBLR4
XAIUGPRBHR4
XAIUGPRAR5
XAIUGPRBLR5
XAIUGPRBHR5
XAIUGPRAR6
XAIUGPRBLR6
XAIUGPRBHR6
XAIUGPRAR7
XAIUGPRBLR7
XAIUGPRBHR7
XAIUGPRAR8
XAIUGPRBLR8
XAIUGPRBHR8
XAIUGPRAR9
XAIUGPRBLR9
XAIUGPRBHR9
XAIUGPRAR10
XAIUGPRBLR10
XAIUGPRBHR10
XAIUGPRAR11
XAIUGPRBLR11
XAIUGPRBHR11
XAIUTBALR0
XAIUTBAHR0
XAIUTOPCR00
XAIUTOPCR10
XAIUTUBR0
XAIUTUBMR0
XAIUCCTRLR
XAIUTCTRLR0
XAIUEDR0
XAIUEDR1
XAIUEDR2
XAIUEDR3
XAIUEDR4
XAIUEDR5
XAIUEDR6
XAIUEDR7
XAIUCNTCR0
XAIUCNTVR0
XAIUCNTSR0
XAIUCNTCR1
XAIUCNTVR1
XAIUCNTSR1
XAIUCNTCR2
XAIUCNTVR2
XAIUCNTSR2
XAIUCNTCR3
XAIUCNTVR3
XAIUCNTSR3
XAIUNRSAR
XAIUENGIDR
XAIUINFOR
TCU Address Map
TCU Summary
XAIUIDR
XAIUFUIDR
XAIUTCR
XAIUTAR
XAIUUEDR
XAIUUEIR
XAIUUESR
XAIUUELR0
XAIUUELR1
XAIUUESAR
XAIUCECR
XAIUCESR
XAIUCELR0
XAIUCELR1
XAIUCESAR
XAIUCRTR
XAIUTOCR
XAIUQOSCR
XAIUQOSSR
XAIUNRSBAR
XAIUNRSBHR
XAIUNRSBLR
XAIUBRAR
XAIUBRBLR
XAIUBRBHR
XAIUAMIGR
XAIUMIFSR
XAIUGPRAR0
XAIUGPRBLR0
XAIUGPRBHR0
XAIUGPRAR1
XAIUGPRBLR1
XAIUGPRBHR1
XAIUGPRAR2
XAIUGPRBLR2
XAIUGPRBHR2
XAIUGPRAR3
XAIUGPRBLR3
XAIUGPRBHR3
XAIUGPRAR4
XAIUGPRBLR4
XAIUGPRBHR4
XAIUGPRAR5
XAIUGPRBLR5
XAIUGPRBHR5
XAIUGPRAR6
XAIUGPRBLR6
XAIUGPRBHR6
XAIUGPRAR7
XAIUGPRBLR7
XAIUGPRBHR7
XAIUGPRAR8
XAIUGPRBLR8
XAIUGPRBHR8
XAIUGPRAR9
XAIUGPRBLR9
XAIUGPRBHR9
XAIUGPRAR10
XAIUGPRBLR10
XAIUGPRBHR10
XAIUGPRAR11
XAIUGPRBLR11
XAIUGPRBHR11
XAIUTBALR0
XAIUTBAHR0
XAIUTOPCR00
XAIUTOPCR10
XAIUTUBR0
XAIUTUBMR0
XAIUCCTRLR
XAIUTCTRLR0
XAIUEDR0
XAIUEDR1
XAIUEDR2
XAIUEDR3
XAIUEDR4
XAIUEDR5
XAIUEDR6
XAIUEDR7
XAIUCNTCR0
XAIUCNTVR0
XAIUCNTSR0
XAIUCNTCR1
XAIUCNTVR1
XAIUCNTSR1
XAIUCNTCR2
XAIUCNTVR2
XAIUCNTSR2
XAIUCNTCR3
XAIUCNTVR3
XAIUCNTSR3
XAIUNRSAR
XAIUENGIDR
XAIUINFOR
CCU_IOM Address Map
CCU_IOM Summary
XAIUIDR
XAIUFUIDR
XAIUTCR
XAIUTAR
XAIUUEDR
XAIUUEIR
XAIUUESR
XAIUUELR0
XAIUUELR1
XAIUUESAR
XAIUCECR
XAIUCESR
XAIUCELR0
XAIUCELR1
XAIUCESAR
XAIUCRTR
XAIUTOCR
XAIUQOSCR
XAIUQOSSR
XAIUNRSBAR
XAIUNRSBHR
XAIUNRSBLR
XAIUBRAR
XAIUBRBLR
XAIUBRBHR
XAIUAMIGR
XAIUMIFSR
XAIUGPRAR0
XAIUGPRBLR0
XAIUGPRBHR0
XAIUGPRAR1
XAIUGPRBLR1
XAIUGPRBHR1
XAIUGPRAR2
XAIUGPRBLR2
XAIUGPRBHR2
XAIUGPRAR3
XAIUGPRBLR3
XAIUGPRBHR3
XAIUGPRAR4
XAIUGPRBLR4
XAIUGPRBHR4
XAIUGPRAR5
XAIUGPRBLR5
XAIUGPRBHR5
XAIUGPRAR6
XAIUGPRBLR6
XAIUGPRBHR6
XAIUGPRAR7
XAIUGPRBLR7
XAIUGPRBHR7
XAIUGPRAR8
XAIUGPRBLR8
XAIUGPRBHR8
XAIUGPRAR9
XAIUGPRBLR9
XAIUGPRBHR9
XAIUGPRAR10
XAIUGPRBLR10
XAIUGPRBHR10
XAIUGPRAR11
XAIUGPRBLR11
XAIUGPRBHR11
XAIUTBALR0
XAIUTBAHR0
XAIUTOPCR00
XAIUTOPCR10
XAIUTUBR0
XAIUTUBMR0
XAIUCCTRLR
XAIUTCTRLR0
XAIUEDR0
XAIUEDR1
XAIUEDR2
XAIUEDR3
XAIUEDR4
XAIUEDR5
XAIUEDR6
XAIUEDR7
XAIUCNTCR0
XAIUCNTVR0
XAIUCNTSR0
XAIUCNTCR1
XAIUCNTVR1
XAIUCNTSR1
XAIUCNTCR2
XAIUCNTVR2
XAIUCNTSR2
XAIUCNTCR3
XAIUCNTVR3
XAIUCNTSR3
XAIUNRSAR
XAIUENGIDR
XAIUINFOR
dce0 Address Map
dce0 Summary
DCEUIDR
DCEUFUIDR
DCEUTCR
DCEUTAR
DCEUSER0
DCEUCECR
DCEUCESR
DCEUCELR0
DCEUCELR1
DCEUCESAR
DCEUUEDR
DCEUUEIR
DCEUUESR
DCEUUELR0
DCEUUELR1
DCEUUESAR
DCEUTOCR
DCEUQOSCR0
DCEUSFMCR
DCEUSFMAR
DCEUBRAR
DCEUBRBLR
DCEUBRBHR
DCEUAMIGR
DCEUMIFSR
DCEUGPRAR0
DCEUGPRBLR0
DCEUGPRBHR0
DCEUGPRAR1
DCEUGPRBLR1
DCEUGPRBHR1
DCEUGPRAR2
DCEUGPRBLR2
DCEUGPRBHR2
DCEUGPRAR3
DCEUGPRBLR3
DCEUGPRBHR3
DCEUGPRAR4
DCEUGPRBLR4
DCEUGPRBHR4
DCEUGPRAR5
DCEUGPRBLR5
DCEUGPRBHR5
DCEUGPRAR6
DCEUGPRBLR6
DCEUGPRBHR6
DCEUGPRAR7
DCEUGPRBLR7
DCEUGPRBHR7
DCEUGPRAR8
DCEUGPRBLR8
DCEUGPRBHR8
DCEUGPRAR9
DCEUGPRBLR9
DCEUGPRBHR9
DCEUGPRAR10
DCEUGPRBLR10
DCEUGPRBHR10
DCEUGPRAR11
DCEUGPRBLR11
DCEUGPRBHR11
DCEUEDR0
DCECNTCR0
DCECNTVR0
DCECNTSR0
DCECNTCR1
DCECNTVR1
DCECNTSR1
DCECNTCR2
DCECNTVR2
DCECNTSR2
DCECNTCR3
DCECNTVR3
DCECNTSR3
DCEUENGIDR
DCEUINFOR
dce1 Address Map
dce1 Summary
DCEUIDR
DCEUFUIDR
DCEUTCR
DCEUTAR
DCEUSER0
DCEUCECR
DCEUCESR
DCEUCELR0
DCEUCELR1
DCEUCESAR
DCEUUEDR
DCEUUEIR
DCEUUESR
DCEUUELR0
DCEUUELR1
DCEUUESAR
DCEUTOCR
DCEUQOSCR0
DCEUSFMCR
DCEUSFMAR
DCEUBRAR
DCEUBRBLR
DCEUBRBHR
DCEUAMIGR
DCEUMIFSR
DCEUGPRAR0
DCEUGPRBLR0
DCEUGPRBHR0
DCEUGPRAR1
DCEUGPRBLR1
DCEUGPRBHR1
DCEUGPRAR2
DCEUGPRBLR2
DCEUGPRBHR2
DCEUGPRAR3
DCEUGPRBLR3
DCEUGPRBHR3
DCEUGPRAR4
DCEUGPRBLR4
DCEUGPRBHR4
DCEUGPRAR5
DCEUGPRBLR5
DCEUGPRBHR5
DCEUGPRAR6
DCEUGPRBLR6
DCEUGPRBHR6
DCEUGPRAR7
DCEUGPRBLR7
DCEUGPRBHR7
DCEUGPRAR8
DCEUGPRBLR8
DCEUGPRBHR8
DCEUGPRAR9
DCEUGPRBLR9
DCEUGPRBHR9
DCEUGPRAR10
DCEUGPRBLR10
DCEUGPRBHR10
DCEUGPRAR11
DCEUGPRBLR11
DCEUGPRBHR11
DCEUEDR0
DCECNTCR0
DCECNTVR0
DCECNTSR0
DCECNTCR1
DCECNTVR1
DCECNTSR1
DCECNTCR2
DCECNTVR2
DCECNTSR2
DCECNTCR3
DCECNTVR3
DCECNTSR3
DCEUENGIDR
DCEUINFOR
CCU_DMI0 Address Map
CCU_DMI0 Summary
DMIUIDR
DMIUFUIDR
DMIUTAR
DMIUUEDR
DMIUUEIR
DMIUUESR
DMIUUELR0
DMIUUELR1
DMIUUESAR
DMIUCECR
DMIUCESR
DMIUCELR0
DMIUCELR1
DMIUCESAR
DMIUTOCR
DMIUQOSCR0
DMIUSMCTCR
DMIUSMCTAR
DMIUSMCAPR
DMIUSMCISR
DMIUSMCMCR
DMIUSMCMAR
DMIUSMCMLR0
DMIUSMCMLR1
DMIUSMCMDR
DMICCTRLR
DMICNTCR0
DMICNTVR0
DMICNTSR0
DMICNTCR1
DMICNTVR1
DMICNTSR1
DMICNTCR2
DMICNTVR2
DMICNTSR2
DMICNTCR3
DMICNTVR3
DMICNTSR3
DMIUEVIDR
DMIUSMCIFR
DMIUINFOR
CCU_DMI1 Address Map
CCU_DMI1 Summary
DMIUIDR
DMIUFUIDR
DMIUTAR
DMIUUEDR
DMIUUEIR
DMIUUESR
DMIUUELR0
DMIUUELR1
DMIUUESAR
DMIUCECR
DMIUCESR
DMIUCELR0
DMIUCELR1
DMIUCESAR
DMIUTOCR
DMIUQOSCR0
DMIUSMCTCR
DMIUSMCTAR
DMIUSMCAPR
DMIUSMCISR
DMIUSMCMCR
DMIUSMCMAR
DMIUSMCMLR0
DMIUSMCMLR1
DMIUSMCMDR
DMICCTRLR
DMICNTCR0
DMICNTVR0
DMICNTSR0
DMICNTCR1
DMICNTVR1
DMICNTSR1
DMICNTCR2
DMICNTVR2
DMICNTSR2
DMICNTCR3
DMICNTVR3
DMICNTSR3
DMIUEVIDR
DMIUSMCIFR
DMIUINFOR
CCU_IOS Address Map
CCU_IOS Summary
DIIUIDR
DIIUFUIDR
DIIUTAR
DIIUUEDR
DIIUUEIR
DIIUUESR
DIIUUELR0
DIIUUELR1
DIIUUESAR
DIICCTRLR
DIICNTCR0
DIICNTVR0
DIICNTSR0
DIICNTCR1
DIICNTVR1
DIICNTSR1
DIICNTCR2
DIICNTVR2
DIICNTSR2
DIICNTCR3
DIICNTVR3
DIICNTSR3
DIIUUEVIR
DIIUINFOR
CCU_MPFE_CSR Address Map
CCU_MPFE_CSR Summary
DIIUIDR
DIIUFUIDR
DIIUTAR
DIIUUEDR
DIIUUEIR
DIIUUESR
DIIUUELR0
DIIUUELR1
DIIUUESAR
DIICCTRLR
DIICNTCR0
DIICNTVR0
DIICNTSR0
DIICNTCR1
DIICNTVR1
DIICNTSR1
DIICNTCR2
DIICNTVR2
DIICNTSR2
DIICNTCR3
DIICNTVR3
DIICNTSR3
DIIUUEVIR
DIIUINFOR
GIC_CSR Address Map
GIC_CSR Summary
DIIUIDR
DIIUFUIDR
DIIUTAR
DIIUUEDR
DIIUUEIR
DIIUUESR
DIIUUELR0
DIIUUELR1
DIIUUESAR
DIICCTRLR
DIICNTCR0
DIICNTVR0
DIICNTSR0
DIICNTCR1
DIICNTVR1
DIICNTSR1
DIICNTCR2
DIICNTVR2
DIICNTSR2
DIICNTCR3
DIICNTVR3
DIICNTSR3
DIIUUEVIR
DIIUINFOR
OCRAM Address Map
OCRAM Summary
DIIUIDR
DIIUFUIDR
DIIUTAR
DIIUUEDR
DIIUUEIR
DIIUUESR
DIIUUELR0
DIIUUELR1
DIIUUESAR
DIICCTRLR
DIICNTCR0
DIICNTVR0
DIICNTSR0
DIICNTCR1
DIICNTVR1
DIICNTSR1
DIICNTCR2
DIICNTVR2
DIICNTSR2
DIICNTCR3
DIICNTVR3
DIICNTSR3
DIIUUEVIR
DIIUINFOR
sys_dii Address Map
sys_dii Summary
DIIUIDR
DIIUFUIDR
DIIUTAR
DIIUUEDR
DIIUUEIR
DIIUUESR
DIIUUELR0
DIIUUELR1
DIIUUESAR
DIICCTRLR
DIICNTCR0
DIICNTVR0
DIICNTSR0
DIICNTCR1
DIICNTVR1
DIICNTSR1
DIICNTCR2
DIICNTVR2
DIICNTSR2
DIICNTCR3
DIICNTVR3
DIICNTSR3
DIIUUEVIR
DIIUINFOR
dve0 Address Map
dve0 Summary
DVEUIDR
DVEUFUIDR
DVEUTAR
DVECECR
DVECESR
DVECELR0
DVECELR1
DVECESAR
DVEUUEDR
DVEUUEIR
DVEUUESR
DVEUUELR0
DVEUUELR1
DVEUUESAR
DVEUCRTR
DVEUSER0
DVETASCR
DVETADHR
DVETADTSR
DVETAD0R
DVETAD1R
DVETAD2R
DVETAD3R
DVETAD4R
DVETAD5R
DVETAD6R
DVETAD7R
DVETAD8R
DVETAD9R
DVETAD10R
DVETAD11R
DVETAD12R
DVETAD13R
DVETAD14R
DVETAD15R
DVECNTCR0
DVECNTVR0
DVECNTSR0
DVECNTCR1
DVECNTVR1
DVECNTSR1
DVECNTCR2
DVECNTVR2
DVECNTSR2
DVECNTCR3
DVECNTVR3
DVECNTSR3
DVEUENGDBR
DVEUENGIDR
DVEUINFOR
sys_global_register_blk Address Map
sys_global_register_blk Summary
GRBUCSSFIDR0
GRBUNRRIR
GRBUENGIDR
GRBUNRRUCR
GRBUNSIDR
GIC Address Block Group
GICD Address Map
GICD Summary
GICD_CTLR
GICD_TYPER
GICD_IIDR
GICD_FCTLR
GICD_SAC
GICD_SETSPI_NSR
GICD_CLRSPI_NSR
GICD_SETSPI_SR
GICD_CLRSPI_SR
GICD_IGROUPR1
GICD_IGROUPR2
GICD_IGROUPR3
GICD_IGROUPR4
GICD_IGROUPR5
GICD_IGROUPR6
GICD_IGROUPR7
GICD_IGROUPR8
GICD_IGROUPR9
GICD_IGROUPR10
GICD_IGROUPR11
GICD_IGROUPR12
GICD_IGROUPR13
GICD_IGROUPR14
GICD_IGROUPR15
GICD_IGROUPR16
GICD_IGROUPR17
GICD_ISENABLER1
GICD_ISENABLER2
GICD_ISENABLER3
GICD_ISENABLER4
GICD_ISENABLER5
GICD_ISENABLER6
GICD_ISENABLER7
GICD_ISENABLER8
GICD_ISENABLER9
GICD_ISENABLER10
GICD_ISENABLER11
GICD_ISENABLER12
GICD_ISENABLER13
GICD_ISENABLER14
GICD_ISENABLER15
GICD_ISENABLER16
GICD_ISENABLER17
GICD_ICENABLER1
GICD_ICENABLER2
GICD_ICENABLER3
GICD_ICENABLER4
GICD_ICENABLER5
GICD_ICENABLER6
GICD_ICENABLER7
GICD_ICENABLER8
GICD_ICENABLER9
GICD_ICENABLER10
GICD_ICENABLER11
GICD_ICENABLER12
GICD_ICENABLER13
GICD_ICENABLER14
GICD_ICENABLER15
GICD_ICENABLER16
GICD_ICENABLER17
GICD_ISPENDR1
GICD_ISPENDR2
GICD_ISPENDR3
GICD_ISPENDR4
GICD_ISPENDR5
GICD_ISPENDR6
GICD_ISPENDR7
GICD_ISPENDR8
GICD_ISPENDR9
GICD_ISPENDR10
GICD_ISPENDR11
GICD_ISPENDR12
GICD_ISPENDR13
GICD_ISPENDR14
GICD_ISPENDR15
GICD_ISPENDR16
GICD_ISPENDR17
GICD_ICPENDR1
GICD_ICPENDR2
GICD_ICPENDR3
GICD_ICPENDR4
GICD_ICPENDR5
GICD_ICPENDR6
GICD_ICPENDR7
GICD_ICPENDR8
GICD_ICPENDR9
GICD_ICPENDR10
GICD_ICPENDR11
GICD_ICPENDR12
GICD_ICPENDR13
GICD_ICPENDR14
GICD_ICPENDR15
GICD_ICPENDR16
GICD_ICPENDR17
GICD_ISACTIVER1
GICD_ISACTIVER2
GICD_ISACTIVER3
GICD_ISACTIVER4
GICD_ISACTIVER5
GICD_ISACTIVER6
GICD_ISACTIVER7
GICD_ISACTIVER8
GICD_ISACTIVER9
GICD_ISACTIVER10
GICD_ISACTIVER11
GICD_ISACTIVER12
GICD_ISACTIVER13
GICD_ISACTIVER14
GICD_ISACTIVER15
GICD_ISACTIVER16
GICD_ISACTIVER17
GICD_ICACTIVER1
GICD_ICACTIVER2
GICD_ICACTIVER3
GICD_ICACTIVER4
GICD_ICACTIVER5
GICD_ICACTIVER6
GICD_ICACTIVER7
GICD_ICACTIVER8
GICD_ICACTIVER9
GICD_ICACTIVER10
GICD_ICACTIVER11
GICD_ICACTIVER12
GICD_ICACTIVER13
GICD_ICACTIVER14
GICD_ICACTIVER15
GICD_ICACTIVER16
GICD_ICACTIVER17
GICD_IPRIORITYR8
GICD_IPRIORITYR9
GICD_IPRIORITYR10
GICD_IPRIORITYR11
GICD_IPRIORITYR12
GICD_IPRIORITYR13
GICD_IPRIORITYR14
GICD_IPRIORITYR15
GICD_IPRIORITYR16
GICD_IPRIORITYR17
GICD_IPRIORITYR18
GICD_IPRIORITYR19
GICD_IPRIORITYR20
GICD_IPRIORITYR21
GICD_IPRIORITYR22
GICD_IPRIORITYR23
GICD_IPRIORITYR24
GICD_IPRIORITYR25
GICD_IPRIORITYR26
GICD_IPRIORITYR27
GICD_IPRIORITYR28
GICD_IPRIORITYR29
GICD_IPRIORITYR30
GICD_IPRIORITYR31
GICD_IPRIORITYR32
GICD_IPRIORITYR33
GICD_IPRIORITYR34
GICD_IPRIORITYR35
GICD_IPRIORITYR36
GICD_IPRIORITYR37
GICD_IPRIORITYR38
GICD_IPRIORITYR39
GICD_IPRIORITYR40
GICD_IPRIORITYR41
GICD_IPRIORITYR42
GICD_IPRIORITYR43
GICD_IPRIORITYR44
GICD_IPRIORITYR45
GICD_IPRIORITYR46
GICD_IPRIORITYR47
GICD_IPRIORITYR48
GICD_IPRIORITYR49
GICD_IPRIORITYR50
GICD_IPRIORITYR51
GICD_IPRIORITYR52
GICD_IPRIORITYR53
GICD_IPRIORITYR54
GICD_IPRIORITYR55
GICD_IPRIORITYR56
GICD_IPRIORITYR57
GICD_IPRIORITYR58
GICD_IPRIORITYR59
GICD_IPRIORITYR60
GICD_IPRIORITYR61
GICD_IPRIORITYR62
GICD_IPRIORITYR63
GICD_IPRIORITYR64
GICD_IPRIORITYR65
GICD_IPRIORITYR66
GICD_IPRIORITYR67
GICD_IPRIORITYR68
GICD_IPRIORITYR69
GICD_IPRIORITYR70
GICD_IPRIORITYR71
GICD_IPRIORITYR72
GICD_IPRIORITYR73
GICD_IPRIORITYR74
GICD_IPRIORITYR75
GICD_IPRIORITYR76
GICD_IPRIORITYR77
GICD_IPRIORITYR78
GICD_IPRIORITYR79
GICD_IPRIORITYR80
GICD_IPRIORITYR81
GICD_IPRIORITYR82
GICD_IPRIORITYR83
GICD_IPRIORITYR84
GICD_IPRIORITYR85
GICD_IPRIORITYR86
GICD_IPRIORITYR87
GICD_IPRIORITYR88
GICD_IPRIORITYR89
GICD_IPRIORITYR90
GICD_IPRIORITYR91
GICD_IPRIORITYR92
GICD_IPRIORITYR93
GICD_IPRIORITYR94
GICD_IPRIORITYR95
GICD_IPRIORITYR96
GICD_IPRIORITYR97
GICD_IPRIORITYR98
GICD_IPRIORITYR99
GICD_IPRIORITYR100
GICD_IPRIORITYR101
GICD_IPRIORITYR102
GICD_IPRIORITYR103
GICD_IPRIORITYR104
GICD_IPRIORITYR105
GICD_IPRIORITYR106
GICD_IPRIORITYR107
GICD_IPRIORITYR108
GICD_IPRIORITYR109
GICD_IPRIORITYR110
GICD_IPRIORITYR111
GICD_IPRIORITYR112
GICD_IPRIORITYR113
GICD_IPRIORITYR114
GICD_IPRIORITYR115
GICD_IPRIORITYR116
GICD_IPRIORITYR117
GICD_IPRIORITYR118
GICD_IPRIORITYR119
GICD_IPRIORITYR120
GICD_IPRIORITYR121
GICD_IPRIORITYR122
GICD_IPRIORITYR123
GICD_IPRIORITYR124
GICD_IPRIORITYR125
GICD_IPRIORITYR126
GICD_IPRIORITYR127
GICD_IPRIORITYR128
GICD_IPRIORITYR129
GICD_IPRIORITYR130
GICD_IPRIORITYR131
GICD_IPRIORITYR132
GICD_IPRIORITYR133
GICD_IPRIORITYR134
GICD_IPRIORITYR135
GICD_IPRIORITYR136
GICD_IPRIORITYR137
GICD_IPRIORITYR138
GICD_IPRIORITYR139
GICD_IPRIORITYR140
GICD_IPRIORITYR141
GICD_IPRIORITYR142
GICD_IPRIORITYR143
GICD_ICFGR2
GICD_ICFGR3
GICD_ICFGR4
GICD_ICFGR5
GICD_ICFGR6
GICD_ICFGR7
GICD_ICFGR8
GICD_ICFGR9
GICD_ICFGR10
GICD_ICFGR11
GICD_ICFGR12
GICD_ICFGR13
GICD_ICFGR14
GICD_ICFGR15
GICD_ICFGR16
GICD_ICFGR17
GICD_ICFGR18
GICD_ICFGR19
GICD_ICFGR20
GICD_ICFGR21
GICD_ICFGR22
GICD_ICFGR23
GICD_ICFGR24
GICD_ICFGR25
GICD_ICFGR26
GICD_ICFGR27
GICD_ICFGR28
GICD_ICFGR29
GICD_ICFGR30
GICD_ICFGR31
GICD_ICFGR32
GICD_ICFGR33
GICD_ICFGR34
GICD_ICFGR35
GICD_IGRPMODR1
GICD_IGRPMODR2
GICD_IGRPMODR3
GICD_IGRPMODR4
GICD_IGRPMODR5
GICD_IGRPMODR6
GICD_IGRPMODR7
GICD_IGRPMODR8
GICD_IGRPMODR9
GICD_IGRPMODR10
GICD_IGRPMODR11
GICD_IGRPMODR12
GICD_IGRPMODR13
GICD_IGRPMODR14
GICD_IGRPMODR15
GICD_IGRPMODR16
GICD_IGRPMODR17
GICD_NSACR2
GICD_NSACR3
GICD_NSACR4
GICD_NSACR5
GICD_NSACR6
GICD_NSACR7
GICD_NSACR8
GICD_NSACR9
GICD_NSACR10
GICD_NSACR11
GICD_NSACR12
GICD_NSACR13
GICD_NSACR14
GICD_NSACR15
GICD_NSACR16
GICD_NSACR17
GICD_NSACR18
GICD_NSACR19
GICD_NSACR20
GICD_NSACR21
GICD_NSACR22
GICD_NSACR23
GICD_NSACR24
GICD_NSACR25
GICD_NSACR26
GICD_NSACR27
GICD_NSACR28
GICD_NSACR29
GICD_NSACR30
GICD_NSACR31
GICD_NSACR32
GICD_NSACR33
GICD_NSACR34
GICD_NSACR35
GICD_IROUTER32
GICD_IROUTER33
GICD_IROUTER34
GICD_IROUTER35
GICD_IROUTER36
GICD_IROUTER37
GICD_IROUTER38
GICD_IROUTER39
GICD_IROUTER40
GICD_IROUTER41
GICD_IROUTER42
GICD_IROUTER43
GICD_IROUTER44
GICD_IROUTER45
GICD_IROUTER46
GICD_IROUTER47
GICD_IROUTER48
GICD_IROUTER49
GICD_IROUTER50
GICD_IROUTER51
GICD_IROUTER52
GICD_IROUTER53
GICD_IROUTER54
GICD_IROUTER55
GICD_IROUTER56
GICD_IROUTER57
GICD_IROUTER58
GICD_IROUTER59
GICD_IROUTER60
GICD_IROUTER61
GICD_IROUTER62
GICD_IROUTER63
GICD_IROUTER64
GICD_IROUTER65
GICD_IROUTER66
GICD_IROUTER67
GICD_IROUTER68
GICD_IROUTER69
GICD_IROUTER70
GICD_IROUTER71
GICD_IROUTER72
GICD_IROUTER73
GICD_IROUTER74
GICD_IROUTER75
GICD_IROUTER76
GICD_IROUTER77
GICD_IROUTER78
GICD_IROUTER79
GICD_IROUTER80
GICD_IROUTER81
GICD_IROUTER82
GICD_IROUTER83
GICD_IROUTER84
GICD_IROUTER85
GICD_IROUTER86
GICD_IROUTER87
GICD_IROUTER88
GICD_IROUTER89
GICD_IROUTER90
GICD_IROUTER91
GICD_IROUTER92
GICD_IROUTER93
GICD_IROUTER94
GICD_IROUTER95
GICD_IROUTER96
GICD_IROUTER97
GICD_IROUTER98
GICD_IROUTER99
GICD_IROUTER100
GICD_IROUTER101
GICD_IROUTER102
GICD_IROUTER103
GICD_IROUTER104
GICD_IROUTER105
GICD_IROUTER106
GICD_IROUTER107
GICD_IROUTER108
GICD_IROUTER109
GICD_IROUTER110
GICD_IROUTER111
GICD_IROUTER112
GICD_IROUTER113
GICD_IROUTER114
GICD_IROUTER115
GICD_IROUTER116
GICD_IROUTER117
GICD_IROUTER118
GICD_IROUTER119
GICD_IROUTER120
GICD_IROUTER121
GICD_IROUTER122
GICD_IROUTER123
GICD_IROUTER124
GICD_IROUTER125
GICD_IROUTER126
GICD_IROUTER127
GICD_IROUTER128
GICD_IROUTER129
GICD_IROUTER130
GICD_IROUTER131
GICD_IROUTER132
GICD_IROUTER133
GICD_IROUTER134
GICD_IROUTER135
GICD_IROUTER136
GICD_IROUTER137
GICD_IROUTER138
GICD_IROUTER139
GICD_IROUTER140
GICD_IROUTER141
GICD_IROUTER142
GICD_IROUTER143
GICD_IROUTER144
GICD_IROUTER145
GICD_IROUTER146
GICD_IROUTER147
GICD_IROUTER148
GICD_IROUTER149
GICD_IROUTER150
GICD_IROUTER151
GICD_IROUTER152
GICD_IROUTER153
GICD_IROUTER154
GICD_IROUTER155
GICD_IROUTER156
GICD_IROUTER157
GICD_IROUTER158
GICD_IROUTER159
GICD_IROUTER160
GICD_IROUTER161
GICD_IROUTER162
GICD_IROUTER163
GICD_IROUTER164
GICD_IROUTER165
GICD_IROUTER166
GICD_IROUTER167
GICD_IROUTER168
GICD_IROUTER169
GICD_IROUTER170
GICD_IROUTER171
GICD_IROUTER172
GICD_IROUTER173
GICD_IROUTER174
GICD_IROUTER175
GICD_IROUTER176
GICD_IROUTER177
GICD_IROUTER178
GICD_IROUTER179
GICD_IROUTER180
GICD_IROUTER181
GICD_IROUTER182
GICD_IROUTER183
GICD_IROUTER184
GICD_IROUTER185
GICD_IROUTER186
GICD_IROUTER187
GICD_IROUTER188
GICD_IROUTER189
GICD_IROUTER190
GICD_IROUTER191
GICD_IROUTER192
GICD_IROUTER193
GICD_IROUTER194
GICD_IROUTER195
GICD_IROUTER196
GICD_IROUTER197
GICD_IROUTER198
GICD_IROUTER199
GICD_IROUTER200
GICD_IROUTER201
GICD_IROUTER202
GICD_IROUTER203
GICD_IROUTER204
GICD_IROUTER205
GICD_IROUTER206
GICD_IROUTER207
GICD_IROUTER208
GICD_IROUTER209
GICD_IROUTER210
GICD_IROUTER211
GICD_IROUTER212
GICD_IROUTER213
GICD_IROUTER214
GICD_IROUTER215
GICD_IROUTER216
GICD_IROUTER217
GICD_IROUTER218
GICD_IROUTER219
GICD_IROUTER220
GICD_IROUTER221
GICD_IROUTER222
GICD_IROUTER223
GICD_IROUTER224
GICD_IROUTER225
GICD_IROUTER226
GICD_IROUTER227
GICD_IROUTER228
GICD_IROUTER229
GICD_IROUTER230
GICD_IROUTER231
GICD_IROUTER232
GICD_IROUTER233
GICD_IROUTER234
GICD_IROUTER235
GICD_IROUTER236
GICD_IROUTER237
GICD_IROUTER238
GICD_IROUTER239
GICD_IROUTER240
GICD_IROUTER241
GICD_IROUTER242
GICD_IROUTER243
GICD_IROUTER244
GICD_IROUTER245
GICD_IROUTER246
GICD_IROUTER247
GICD_IROUTER248
GICD_IROUTER249
GICD_IROUTER250
GICD_IROUTER251
GICD_IROUTER252
GICD_IROUTER253
GICD_IROUTER254
GICD_IROUTER255
GICD_IROUTER256
GICD_IROUTER257
GICD_IROUTER258
GICD_IROUTER259
GICD_IROUTER260
GICD_IROUTER261
GICD_IROUTER262
GICD_IROUTER263
GICD_IROUTER264
GICD_IROUTER265
GICD_IROUTER266
GICD_IROUTER267
GICD_IROUTER268
GICD_IROUTER269
GICD_IROUTER270
GICD_IROUTER271
GICD_IROUTER272
GICD_IROUTER273
GICD_IROUTER274
GICD_IROUTER275
GICD_IROUTER276
GICD_IROUTER277
GICD_IROUTER278
GICD_IROUTER279
GICD_IROUTER280
GICD_IROUTER281
GICD_IROUTER282
GICD_IROUTER283
GICD_IROUTER284
GICD_IROUTER285
GICD_IROUTER286
GICD_IROUTER287
GICD_IROUTER288
GICD_IROUTER289
GICD_IROUTER290
GICD_IROUTER291
GICD_IROUTER292
GICD_IROUTER293
GICD_IROUTER294
GICD_IROUTER295
GICD_IROUTER296
GICD_IROUTER297
GICD_IROUTER298
GICD_IROUTER299
GICD_IROUTER300
GICD_IROUTER301
GICD_IROUTER302
GICD_IROUTER303
GICD_IROUTER304
GICD_IROUTER305
GICD_IROUTER306
GICD_IROUTER307
GICD_IROUTER308
GICD_IROUTER309
GICD_IROUTER310
GICD_IROUTER311
GICD_IROUTER312
GICD_IROUTER313
GICD_IROUTER314
GICD_IROUTER315
GICD_IROUTER316
GICD_IROUTER317
GICD_IROUTER318
GICD_IROUTER319
GICD_IROUTER320
GICD_IROUTER321
GICD_IROUTER322
GICD_IROUTER323
GICD_IROUTER324
GICD_IROUTER325
GICD_IROUTER326
GICD_IROUTER327
GICD_IROUTER328
GICD_IROUTER329
GICD_IROUTER330
GICD_IROUTER331
GICD_IROUTER332
GICD_IROUTER333
GICD_IROUTER334
GICD_IROUTER335
GICD_IROUTER336
GICD_IROUTER337
GICD_IROUTER338
GICD_IROUTER339
GICD_IROUTER340
GICD_IROUTER341
GICD_IROUTER342
GICD_IROUTER343
GICD_IROUTER344
GICD_IROUTER345
GICD_IROUTER346
GICD_IROUTER347
GICD_IROUTER348
GICD_IROUTER349
GICD_IROUTER350
GICD_IROUTER351
GICD_IROUTER352
GICD_IROUTER353
GICD_IROUTER354
GICD_IROUTER355
GICD_IROUTER356
GICD_IROUTER357
GICD_IROUTER358
GICD_IROUTER359
GICD_IROUTER360
GICD_IROUTER361
GICD_IROUTER362
GICD_IROUTER363
GICD_IROUTER364
GICD_IROUTER365
GICD_IROUTER366
GICD_IROUTER367
GICD_IROUTER368
GICD_IROUTER369
GICD_IROUTER370
GICD_IROUTER371
GICD_IROUTER372
GICD_IROUTER373
GICD_IROUTER374
GICD_IROUTER375
GICD_IROUTER376
GICD_IROUTER377
GICD_IROUTER378
GICD_IROUTER379
GICD_IROUTER380
GICD_IROUTER381
GICD_IROUTER382
GICD_IROUTER383
GICD_IROUTER384
GICD_IROUTER385
GICD_IROUTER386
GICD_IROUTER387
GICD_IROUTER388
GICD_IROUTER389
GICD_IROUTER390
GICD_IROUTER391
GICD_IROUTER392
GICD_IROUTER393
GICD_IROUTER394
GICD_IROUTER395
GICD_IROUTER396
GICD_IROUTER397
GICD_IROUTER398
GICD_IROUTER399
GICD_IROUTER400
GICD_IROUTER401
GICD_IROUTER402
GICD_IROUTER403
GICD_IROUTER404
GICD_IROUTER405
GICD_IROUTER406
GICD_IROUTER407
GICD_IROUTER408
GICD_IROUTER409
GICD_IROUTER410
GICD_IROUTER411
GICD_IROUTER412
GICD_IROUTER413
GICD_IROUTER414
GICD_IROUTER415
GICD_IROUTER416
GICD_IROUTER417
GICD_IROUTER418
GICD_IROUTER419
GICD_IROUTER420
GICD_IROUTER421
GICD_IROUTER422
GICD_IROUTER423
GICD_IROUTER424
GICD_IROUTER425
GICD_IROUTER426
GICD_IROUTER427
GICD_IROUTER428
GICD_IROUTER429
GICD_IROUTER430
GICD_IROUTER431
GICD_IROUTER432
GICD_IROUTER433
GICD_IROUTER434
GICD_IROUTER435
GICD_IROUTER436
GICD_IROUTER437
GICD_IROUTER438
GICD_IROUTER439
GICD_IROUTER440
GICD_IROUTER441
GICD_IROUTER442
GICD_IROUTER443
GICD_IROUTER444
GICD_IROUTER445
GICD_IROUTER446
GICD_IROUTER447
GICD_IROUTER448
GICD_IROUTER449
GICD_IROUTER450
GICD_IROUTER451
GICD_IROUTER452
GICD_IROUTER453
GICD_IROUTER454
GICD_IROUTER455
GICD_IROUTER456
GICD_IROUTER457
GICD_IROUTER458
GICD_IROUTER459
GICD_IROUTER460
GICD_IROUTER461
GICD_IROUTER462
GICD_IROUTER463
GICD_IROUTER464
GICD_IROUTER465
GICD_IROUTER466
GICD_IROUTER467
GICD_IROUTER468
GICD_IROUTER469
GICD_IROUTER470
GICD_IROUTER471
GICD_IROUTER472
GICD_IROUTER473
GICD_IROUTER474
GICD_IROUTER475
GICD_IROUTER476
GICD_IROUTER477
GICD_IROUTER478
GICD_IROUTER479
GICD_IROUTER480
GICD_IROUTER481
GICD_IROUTER482
GICD_IROUTER483
GICD_IROUTER484
GICD_IROUTER485
GICD_IROUTER486
GICD_IROUTER487
GICD_IROUTER488
GICD_IROUTER489
GICD_IROUTER490
GICD_IROUTER491
GICD_IROUTER492
GICD_IROUTER493
GICD_IROUTER494
GICD_IROUTER495
GICD_IROUTER496
GICD_IROUTER497
GICD_IROUTER498
GICD_IROUTER499
GICD_IROUTER500
GICD_IROUTER501
GICD_IROUTER502
GICD_IROUTER503
GICD_IROUTER504
GICD_IROUTER505
GICD_IROUTER506
GICD_IROUTER507
GICD_IROUTER508
GICD_IROUTER509
GICD_IROUTER510
GICD_IROUTER511
GICD_IROUTER512
GICD_IROUTER513
GICD_IROUTER514
GICD_IROUTER515
GICD_IROUTER516
GICD_IROUTER517
GICD_IROUTER518
GICD_IROUTER519
GICD_IROUTER520
GICD_IROUTER521
GICD_IROUTER522
GICD_IROUTER523
GICD_IROUTER524
GICD_IROUTER525
GICD_IROUTER526
GICD_IROUTER527
GICD_IROUTER528
GICD_IROUTER529
GICD_IROUTER530
GICD_IROUTER531
GICD_IROUTER532
GICD_IROUTER533
GICD_IROUTER534
GICD_IROUTER535
GICD_IROUTER536
GICD_IROUTER537
GICD_IROUTER538
GICD_IROUTER539
GICD_IROUTER540
GICD_IROUTER541
GICD_IROUTER542
GICD_IROUTER543
GICD_IROUTER544
GICD_IROUTER545
GICD_IROUTER546
GICD_IROUTER547
GICD_IROUTER548
GICD_IROUTER549
GICD_IROUTER550
GICD_IROUTER551
GICD_IROUTER552
GICD_IROUTER553
GICD_IROUTER554
GICD_IROUTER555
GICD_IROUTER556
GICD_IROUTER557
GICD_IROUTER558
GICD_IROUTER559
GICD_IROUTER560
GICD_IROUTER561
GICD_IROUTER562
GICD_IROUTER563
GICD_IROUTER564
GICD_IROUTER565
GICD_IROUTER566
GICD_IROUTER567
GICD_IROUTER568
GICD_IROUTER569
GICD_IROUTER570
GICD_IROUTER571
GICD_IROUTER572
GICD_IROUTER573
GICD_IROUTER574
GICD_IROUTER575
GICD_ICLAR2
GICD_ICLAR3
GICD_ICLAR4
GICD_ICLAR5
GICD_ICLAR6
GICD_ICLAR7
GICD_ICLAR8
GICD_ICLAR9
GICD_ICLAR10
GICD_ICLAR11
GICD_ICLAR12
GICD_ICLAR13
GICD_ICLAR14
GICD_ICLAR15
GICD_ICLAR16
GICD_ICLAR17
GICD_ICLAR18
GICD_ICLAR19
GICD_ICLAR20
GICD_ICLAR21
GICD_ICLAR22
GICD_ICLAR23
GICD_ICLAR24
GICD_ICLAR25
GICD_ICLAR26
GICD_ICLAR27
GICD_ICLAR28
GICD_ICLAR29
GICD_ICLAR30
GICD_ICLAR31
GICD_ICLAR32
GICD_ICLAR33
GICD_ICLAR34
GICD_ICLAR35
GICD_IERRR1
GICD_IERRR2
GICD_IERRR3
GICD_IERRR4
GICD_IERRR5
GICD_IERRR6
GICD_IERRR7
GICD_IERRR8
GICD_IERRR9
GICD_IERRR10
GICD_IERRR11
GICD_IERRR12
GICD_IERRR13
GICD_IERRR14
GICD_IERRR15
GICD_IERRR16
GICD_IERRR17
GICD_CFGID
GICD_PIDR4
GICD_PIDR5
GICD_PIDR6
GICD_PIDR7
GICD_PIDR0
GICD_PIDR1
GICD_PIDR2
GICD_PIDR3
GICD_CIDR0
GICD_CIDR1
GICD_CIDR2
GICD_CIDR3
GICA Address Map
GICA Summary
GICA_SETSPI_NSR
GICA_CLRSPI_NSR
GICA_SETSPI_SR
GICA_CLRSPI_SR
GICT Address Map
GICT Summary
GICT_ERR0FR
GICT_ERR0CTLR
GICT_ERR0STATUS
GICT_ERR0ADDR
GICT_ERR0MISC0
GICT_ERR0MISC1
GICT_ERR1FR
GICT_ERR1CTLR
GICT_ERR1STATUS
GICT_ERR1MISC0
GICT_ERR1MISC1
GICT_ERR2FR
GICT_ERR2CTLR
GICT_ERR2STATUS
GICT_ERR2MISC0
GICT_ERR2MISC1
GICT_ERR3FR
GICT_ERR3CTLR
GICT_ERR3STATUS
GICT_ERR3MISC0
GICT_ERR3MISC1
GICT_ERR4FR
GICT_ERR4CTLR
GICT_ERR4STATUS
GICT_ERR4MISC0
GICT_ERR4MISC1
GICT_ERR5FR
GICT_ERR5CTLR
GICT_ERR5STATUS
GICT_ERR5MISC0
GICT_ERR5MISC1
GICT_ERR6FR
GICT_ERR6CTLR
GICT_ERR6STATUS
GICT_ERR6MISC0
GICT_ERR6MISC1
GICT_ERR7FR
GICT_ERR7CTLR
GICT_ERR7STATUS
GICT_ERR7MISC0
GICT_ERR7MISC1
GICT_ERR8FR
GICT_ERR8CTLR
GICT_ERR8STATUS
GICT_ERR8MISC0
GICT_ERR8MISC1
GICT_ERR9FR
GICT_ERR9CTLR
GICT_ERR9STATUS
GICT_ERR9MISC0
GICT_ERR9MISC1
GICT_ERR10FR
GICT_ERR10CTLR
GICT_ERR10STATUS
GICT_ERR10MISC0
GICT_ERR10MISC1
GICT_ERR11FR
GICT_ERR11CTLR
GICT_ERR11STATUS
GICT_ERR11MISC0
GICT_ERR11MISC1
GICT_ERR12FR
GICT_ERR12CTLR
GICT_ERR12STATUS
GICT_ERR12MISC0
GICT_ERR12MISC1
GICT_ERR13FR
GICT_ERR13CTLR
GICT_ERR13STATUS
GICT_ERR13MISC0
GICT_ERR13MISC1
GICT_ERRGSR0
GICT_ERRIRQCR0
GICT_ERRIRQCR1
GICT_DEVARCH
GICT_DEVID
GICT_PIDR4
GICT_PIDR5
GICT_PIDR6
GICT_PIDR7
GICT_PIDR0
GICT_PIDR1
GICT_PIDR2
GICT_PIDR3
GICT_CIDR0
GICT_CIDR1
GICT_CIDR2
GICT_CIDR3
GICP Address Map
GICP Summary
GICP_EVCNTR0
GICP_EVCNTR1
GICP_EVCNTR2
GICP_EVCNTR3
GICP_EVCNTR4
GICP_EVTYPER0
GICP_EVTYPER1
GICP_EVTYPER2
GICP_EVTYPER3
GICP_EVTYPER4
GICP_SVR0
GICP_SVR1
GICP_SVR2
GICP_SVR3
GICP_SVR4
GICP_FR0
GICP_FR1
GICP_FR2
GICP_FR3
GICP_FR4
GICP_CNTENSET0
GICP_CNTENCLR0
GICP_INTENSET0
GICP_INTENCLR0
GICP_OVSCLR0
GICP_OVSSET0
GICP_CAPR
GICP_CFGR
GICP_CR
GICP_IRQCR
GICP_PMAUTHSTATUS
GICP_PMDEVARCH
GICP_PMDEVTYPE
GICP_PIDR4
GICP_PIDR5
GICP_PIDR6
GICP_PIDR7
GICP_PIDR0
GICP_PIDR1
GICP_PIDR2
GICP_PIDR3
GICP_CIDR0
GICP_CIDR1
GICP_CIDR2
GICP_CIDR3
GITS0 Address Map
GITS0 Summary
GITS0_CTLR
GITS0_IIDR
GITS0_TYPER
GITS0_FCTLR
GITS0_OPR
GITS0_OPSR
GITS0_CBASER
GITS0_CWRITER
GITS0_CREADR
GITS0_BASER0
GITS0_BASER1
GITS0_CFGID
GITS0_PIDR4
GITS0_PIDR5
GITS0_PIDR6
GITS0_PIDR7
GITS0_PIDR0
GITS0_PIDR1
GITS0_PIDR2
GITS0_PIDR3
GITS0_CIDR0
GITS0_CIDR1
GITS0_CIDR2
GITS0_CIDR3
GITS0translator Address Map
GITS0translator Summary
GITS0_TRANSLATER
Rlpi0 Address Map
Rlpi0 Summary
GICR0_CTLR
GICR0_IIDR
GICR0_TYPER
GICR0_WAKER
GICR0_FCTLR
GICR0_PWRR
GICR0_CLASS
GICR0_PROPBASER
GICR0_PENDBASER
GICR0_PIDR4
GICR0_PIDR5
GICR0_PIDR6
GICR0_PIDR7
GICR0_PIDR0
GICR0_PIDR1
GICR0_PIDR2
GICR0_PIDR3
GICR0_CIDR0
GICR0_CIDR1
GICR0_CIDR2
GICR0_CIDR3
Rsgi0 Address Map
Rsgi0 Summary
GICR0_IGROUPR0
GICR0_ISENABLER0
GICR0_ICENABLER0
GICR0_ISPENDR0
GICR0_ICPENDR0
GICR0_ISACTIVER0
GICR0_ICACTIVER0
GICR0_IPRIORITYR0
GICR0_IPRIORITYR1
GICR0_IPRIORITYR2
GICR0_IPRIORITYR3
GICR0_IPRIORITYR4
GICR0_IPRIORITYR5
GICR0_IPRIORITYR6
GICR0_IPRIORITYR7
GICR0_ICFGR0
GICR0_ICFGR1
GICR0_IGRPMODR0
GICR0_NSACR
GICR0_MISCSTATUSR
GICR0_IERRVR
GICR0_SGIDR
GICR0_CFGID0
GICR0_CFGID1
Rlpi1 Address Map
Rlpi1 Summary
GICR1_CTLR
GICR1_IIDR
GICR1_TYPER
GICR1_WAKER
GICR1_FCTLR
GICR1_PWRR
GICR1_CLASS
GICR1_PROPBASER
GICR1_PENDBASER
GICR1_PIDR4
GICR1_PIDR5
GICR1_PIDR6
GICR1_PIDR7
GICR1_PIDR0
GICR1_PIDR1
GICR1_PIDR2
GICR1_PIDR3
GICR1_CIDR0
GICR1_CIDR1
GICR1_CIDR2
GICR1_CIDR3
Rsgi1 Address Map
Rsgi1 Summary
GICR1_IGROUPR0
GICR1_ISENABLER0
GICR1_ICENABLER0
GICR1_ISPENDR0
GICR1_ICPENDR0
GICR1_ISACTIVER0
GICR1_ICACTIVER0
GICR1_IPRIORITYR0
GICR1_IPRIORITYR1
GICR1_IPRIORITYR2
GICR1_IPRIORITYR3
GICR1_IPRIORITYR4
GICR1_IPRIORITYR5
GICR1_IPRIORITYR6
GICR1_IPRIORITYR7
GICR1_ICFGR0
GICR1_ICFGR1
GICR1_IGRPMODR0
GICR1_NSACR
GICR1_MISCSTATUSR
GICR1_IERRVR
GICR1_SGIDR
GICR1_CFGID0
GICR1_CFGID1
Rlpi2 Address Map
Rlpi2 Summary
GICR2_CTLR
GICR2_IIDR
GICR2_TYPER
GICR2_WAKER
GICR2_FCTLR
GICR2_PWRR
GICR2_CLASS
GICR2_PROPBASER
GICR2_PENDBASER
GICR2_PIDR4
GICR2_PIDR5
GICR2_PIDR6
GICR2_PIDR7
GICR2_PIDR0
GICR2_PIDR1
GICR2_PIDR2
GICR2_PIDR3
GICR2_CIDR0
GICR2_CIDR1
GICR2_CIDR2
GICR2_CIDR3
Rsgi2 Address Map
Rsgi2 Summary
GICR2_IGROUPR0
GICR2_ISENABLER0
GICR2_ICENABLER0
GICR2_ISPENDR0
GICR2_ICPENDR0
GICR2_ISACTIVER0
GICR2_ICACTIVER0
GICR2_IPRIORITYR0
GICR2_IPRIORITYR1
GICR2_IPRIORITYR2
GICR2_IPRIORITYR3
GICR2_IPRIORITYR4
GICR2_IPRIORITYR5
GICR2_IPRIORITYR6
GICR2_IPRIORITYR7
GICR2_ICFGR0
GICR2_ICFGR1
GICR2_IGRPMODR0
GICR2_NSACR
GICR2_MISCSTATUSR
GICR2_IERRVR
GICR2_SGIDR
GICR2_CFGID0
GICR2_CFGID1
Rlpi3 Address Map
Rlpi3 Summary
GICR3_CTLR
GICR3_IIDR
GICR3_TYPER
GICR3_WAKER
GICR3_FCTLR
GICR3_PWRR
GICR3_CLASS
GICR3_PROPBASER
GICR3_PENDBASER
GICR3_PIDR4
GICR3_PIDR5
GICR3_PIDR6
GICR3_PIDR7
GICR3_PIDR0
GICR3_PIDR1
GICR3_PIDR2
GICR3_PIDR3
GICR3_CIDR0
GICR3_CIDR1
GICR3_CIDR2
GICR3_CIDR3
Rsgi3 Address Map
Rsgi3 Summary
GICR3_IGROUPR0
GICR3_ISENABLER0
GICR3_ICENABLER0
GICR3_ISPENDR0
GICR3_ICPENDR0
GICR3_ISACTIVER0
GICR3_ICACTIVER0
GICR3_IPRIORITYR0
GICR3_IPRIORITYR1
GICR3_IPRIORITYR2
GICR3_IPRIORITYR3
GICR3_IPRIORITYR4
GICR3_IPRIORITYR5
GICR3_IPRIORITYR6
GICR3_IPRIORITYR7
GICR3_ICFGR0
GICR3_ICFGR1
GICR3_IGRPMODR0
GICR3_NSACR
GICR3_MISCSTATUSR
GICR3_IERRVR
GICR3_SGIDR
GICR3_CFGID0
GICR3_CFGID1
GICDA Address Map
GICDA Summary
GICDA_CTLR
GICDA_TYPER
GICDA_IIDR
GICDA_FCTLR
GICDA_SAC
GICDA_SETSPI_NSR
GICDA_CLRSPI_NSR
GICDA_SETSPI_SR
GICDA_CLRSPI_SR
GICDA_IGROUPR1
GICDA_IGROUPR2
GICDA_IGROUPR3
GICDA_IGROUPR4
GICDA_IGROUPR5
GICDA_IGROUPR6
GICDA_IGROUPR7
GICDA_IGROUPR8
GICDA_IGROUPR9
GICDA_IGROUPR10
GICDA_IGROUPR11
GICDA_IGROUPR12
GICDA_IGROUPR13
GICDA_IGROUPR14
GICDA_IGROUPR15
GICDA_IGROUPR16
GICDA_IGROUPR17
GICDA_ISENABLER1
GICDA_ISENABLER2
GICDA_ISENABLER3
GICDA_ISENABLER4
GICDA_ISENABLER5
GICDA_ISENABLER6
GICDA_ISENABLER7
GICDA_ISENABLER8
GICDA_ISENABLER9
GICDA_ISENABLER10
GICDA_ISENABLER11
GICDA_ISENABLER12
GICDA_ISENABLER13
GICDA_ISENABLER14
GICDA_ISENABLER15
GICDA_ISENABLER16
GICDA_ISENABLER17
GICDA_ICENABLER1
GICDA_ICENABLER2
GICDA_ICENABLER3
GICDA_ICENABLER4
GICDA_ICENABLER5
GICDA_ICENABLER6
GICDA_ICENABLER7
GICDA_ICENABLER8
GICDA_ICENABLER9
GICDA_ICENABLER10
GICDA_ICENABLER11
GICDA_ICENABLER12
GICDA_ICENABLER13
GICDA_ICENABLER14
GICDA_ICENABLER15
GICDA_ICENABLER16
GICDA_ICENABLER17
GICDA_ISPENDR1
GICDA_ISPENDR2
GICDA_ISPENDR3
GICDA_ISPENDR4
GICDA_ISPENDR5
GICDA_ISPENDR6
GICDA_ISPENDR7
GICDA_ISPENDR8
GICDA_ISPENDR9
GICDA_ISPENDR10
GICDA_ISPENDR11
GICDA_ISPENDR12
GICDA_ISPENDR13
GICDA_ISPENDR14
GICDA_ISPENDR15
GICDA_ISPENDR16
GICDA_ISPENDR17
GICDA_ICPENDR1
GICDA_ICPENDR2
GICDA_ICPENDR3
GICDA_ICPENDR4
GICDA_ICPENDR5
GICDA_ICPENDR6
GICDA_ICPENDR7
GICDA_ICPENDR8
GICDA_ICPENDR9
GICDA_ICPENDR10
GICDA_ICPENDR11
GICDA_ICPENDR12
GICDA_ICPENDR13
GICDA_ICPENDR14
GICDA_ICPENDR15
GICDA_ICPENDR16
GICDA_ICPENDR17
GICDA_ISACTIVER1
GICDA_ISACTIVER2
GICDA_ISACTIVER3
GICDA_ISACTIVER4
GICDA_ISACTIVER5
GICDA_ISACTIVER6
GICDA_ISACTIVER7
GICDA_ISACTIVER8
GICDA_ISACTIVER9
GICDA_ISACTIVER10
GICDA_ISACTIVER11
GICDA_ISACTIVER12
GICDA_ISACTIVER13
GICDA_ISACTIVER14
GICDA_ISACTIVER15
GICDA_ISACTIVER16
GICDA_ISACTIVER17
GICDA_ICACTIVER1
GICDA_ICACTIVER2
GICDA_ICACTIVER3
GICDA_ICACTIVER4
GICDA_ICACTIVER5
GICDA_ICACTIVER6
GICDA_ICACTIVER7
GICDA_ICACTIVER8
GICDA_ICACTIVER9
GICDA_ICACTIVER10
GICDA_ICACTIVER11
GICDA_ICACTIVER12
GICDA_ICACTIVER13
GICDA_ICACTIVER14
GICDA_ICACTIVER15
GICDA_ICACTIVER16
GICDA_ICACTIVER17
GICDA_IPRIORITYR8
GICDA_IPRIORITYR9
GICDA_IPRIORITYR10
GICDA_IPRIORITYR11
GICDA_IPRIORITYR12
GICDA_IPRIORITYR13
GICDA_IPRIORITYR14
GICDA_IPRIORITYR15
GICDA_IPRIORITYR16
GICDA_IPRIORITYR17
GICDA_IPRIORITYR18
GICDA_IPRIORITYR19
GICDA_IPRIORITYR20
GICDA_IPRIORITYR21
GICDA_IPRIORITYR22
GICDA_IPRIORITYR23
GICDA_IPRIORITYR24
GICDA_IPRIORITYR25
GICDA_IPRIORITYR26
GICDA_IPRIORITYR27
GICDA_IPRIORITYR28
GICDA_IPRIORITYR29
GICDA_IPRIORITYR30
GICDA_IPRIORITYR31
GICDA_IPRIORITYR32
GICDA_IPRIORITYR33
GICDA_IPRIORITYR34
GICDA_IPRIORITYR35
GICDA_IPRIORITYR36
GICDA_IPRIORITYR37
GICDA_IPRIORITYR38
GICDA_IPRIORITYR39
GICDA_IPRIORITYR40
GICDA_IPRIORITYR41
GICDA_IPRIORITYR42
GICDA_IPRIORITYR43
GICDA_IPRIORITYR44
GICDA_IPRIORITYR45
GICDA_IPRIORITYR46
GICDA_IPRIORITYR47
GICDA_IPRIORITYR48
GICDA_IPRIORITYR49
GICDA_IPRIORITYR50
GICDA_IPRIORITYR51
GICDA_IPRIORITYR52
GICDA_IPRIORITYR53
GICDA_IPRIORITYR54
GICDA_IPRIORITYR55
GICDA_IPRIORITYR56
GICDA_IPRIORITYR57
GICDA_IPRIORITYR58
GICDA_IPRIORITYR59
GICDA_IPRIORITYR60
GICDA_IPRIORITYR61
GICDA_IPRIORITYR62
GICDA_IPRIORITYR63
GICDA_IPRIORITYR64
GICDA_IPRIORITYR65
GICDA_IPRIORITYR66
GICDA_IPRIORITYR67
GICDA_IPRIORITYR68
GICDA_IPRIORITYR69
GICDA_IPRIORITYR70
GICDA_IPRIORITYR71
GICDA_IPRIORITYR72
GICDA_IPRIORITYR73
GICDA_IPRIORITYR74
GICDA_IPRIORITYR75
GICDA_IPRIORITYR76
GICDA_IPRIORITYR77
GICDA_IPRIORITYR78
GICDA_IPRIORITYR79
GICDA_IPRIORITYR80
GICDA_IPRIORITYR81
GICDA_IPRIORITYR82
GICDA_IPRIORITYR83
GICDA_IPRIORITYR84
GICDA_IPRIORITYR85
GICDA_IPRIORITYR86
GICDA_IPRIORITYR87
GICDA_IPRIORITYR88
GICDA_IPRIORITYR89
GICDA_IPRIORITYR90
GICDA_IPRIORITYR91
GICDA_IPRIORITYR92
GICDA_IPRIORITYR93
GICDA_IPRIORITYR94
GICDA_IPRIORITYR95
GICDA_IPRIORITYR96
GICDA_IPRIORITYR97
GICDA_IPRIORITYR98
GICDA_IPRIORITYR99
GICDA_IPRIORITYR100
GICDA_IPRIORITYR101
GICDA_IPRIORITYR102
GICDA_IPRIORITYR103
GICDA_IPRIORITYR104
GICDA_IPRIORITYR105
GICDA_IPRIORITYR106
GICDA_IPRIORITYR107
GICDA_IPRIORITYR108
GICDA_IPRIORITYR109
GICDA_IPRIORITYR110
GICDA_IPRIORITYR111
GICDA_IPRIORITYR112
GICDA_IPRIORITYR113
GICDA_IPRIORITYR114
GICDA_IPRIORITYR115
GICDA_IPRIORITYR116
GICDA_IPRIORITYR117
GICDA_IPRIORITYR118
GICDA_IPRIORITYR119
GICDA_IPRIORITYR120
GICDA_IPRIORITYR121
GICDA_IPRIORITYR122
GICDA_IPRIORITYR123
GICDA_IPRIORITYR124
GICDA_IPRIORITYR125
GICDA_IPRIORITYR126
GICDA_IPRIORITYR127
GICDA_IPRIORITYR128
GICDA_IPRIORITYR129
GICDA_IPRIORITYR130
GICDA_IPRIORITYR131
GICDA_IPRIORITYR132
GICDA_IPRIORITYR133
GICDA_IPRIORITYR134
GICDA_IPRIORITYR135
GICDA_IPRIORITYR136
GICDA_IPRIORITYR137
GICDA_IPRIORITYR138
GICDA_IPRIORITYR139
GICDA_IPRIORITYR140
GICDA_IPRIORITYR141
GICDA_IPRIORITYR142
GICDA_IPRIORITYR143
GICDA_ICFGR2
GICDA_ICFGR3
GICDA_ICFGR4
GICDA_ICFGR5
GICDA_ICFGR6
GICDA_ICFGR7
GICDA_ICFGR8
GICDA_ICFGR9
GICDA_ICFGR10
GICDA_ICFGR11
GICDA_ICFGR12
GICDA_ICFGR13
GICDA_ICFGR14
GICDA_ICFGR15
GICDA_ICFGR16
GICDA_ICFGR17
GICDA_ICFGR18
GICDA_ICFGR19
GICDA_ICFGR20
GICDA_ICFGR21
GICDA_ICFGR22
GICDA_ICFGR23
GICDA_ICFGR24
GICDA_ICFGR25
GICDA_ICFGR26
GICDA_ICFGR27
GICDA_ICFGR28
GICDA_ICFGR29
GICDA_ICFGR30
GICDA_ICFGR31
GICDA_ICFGR32
GICDA_ICFGR33
GICDA_ICFGR34
GICDA_ICFGR35
GICDA_IGRPMODR1
GICDA_IGRPMODR2
GICDA_IGRPMODR3
GICDA_IGRPMODR4
GICDA_IGRPMODR5
GICDA_IGRPMODR6
GICDA_IGRPMODR7
GICDA_IGRPMODR8
GICDA_IGRPMODR9
GICDA_IGRPMODR10
GICDA_IGRPMODR11
GICDA_IGRPMODR12
GICDA_IGRPMODR13
GICDA_IGRPMODR14
GICDA_IGRPMODR15
GICDA_IGRPMODR16
GICDA_IGRPMODR17
GICDA_NSACR2
GICDA_NSACR3
GICDA_NSACR4
GICDA_NSACR5
GICDA_NSACR6
GICDA_NSACR7
GICDA_NSACR8
GICDA_NSACR9
GICDA_NSACR10
GICDA_NSACR11
GICDA_NSACR12
GICDA_NSACR13
GICDA_NSACR14
GICDA_NSACR15
GICDA_NSACR16
GICDA_NSACR17
GICDA_NSACR18
GICDA_NSACR19
GICDA_NSACR20
GICDA_NSACR21
GICDA_NSACR22
GICDA_NSACR23
GICDA_NSACR24
GICDA_NSACR25
GICDA_NSACR26
GICDA_NSACR27
GICDA_NSACR28
GICDA_NSACR29
GICDA_NSACR30
GICDA_NSACR31
GICDA_NSACR32
GICDA_NSACR33
GICDA_NSACR34
GICDA_NSACR35
GICDA_IROUTER32
GICDA_IROUTER33
GICDA_IROUTER34
GICDA_IROUTER35
GICDA_IROUTER36
GICDA_IROUTER37
GICDA_IROUTER38
GICDA_IROUTER39
GICDA_IROUTER40
GICDA_IROUTER41
GICDA_IROUTER42
GICDA_IROUTER43
GICDA_IROUTER44
GICDA_IROUTER45
GICDA_IROUTER46
GICDA_IROUTER47
GICDA_IROUTER48
GICDA_IROUTER49
GICDA_IROUTER50
GICDA_IROUTER51
GICDA_IROUTER52
GICDA_IROUTER53
GICDA_IROUTER54
GICDA_IROUTER55
GICDA_IROUTER56
GICDA_IROUTER57
GICDA_IROUTER58
GICDA_IROUTER59
GICDA_IROUTER60
GICDA_IROUTER61
GICDA_IROUTER62
GICDA_IROUTER63
GICDA_IROUTER64
GICDA_IROUTER65
GICDA_IROUTER66
GICDA_IROUTER67
GICDA_IROUTER68
GICDA_IROUTER69
GICDA_IROUTER70
GICDA_IROUTER71
GICDA_IROUTER72
GICDA_IROUTER73
GICDA_IROUTER74
GICDA_IROUTER75
GICDA_IROUTER76
GICDA_IROUTER77
GICDA_IROUTER78
GICDA_IROUTER79
GICDA_IROUTER80
GICDA_IROUTER81
GICDA_IROUTER82
GICDA_IROUTER83
GICDA_IROUTER84
GICDA_IROUTER85
GICDA_IROUTER86
GICDA_IROUTER87
GICDA_IROUTER88
GICDA_IROUTER89
GICDA_IROUTER90
GICDA_IROUTER91
GICDA_IROUTER92
GICDA_IROUTER93
GICDA_IROUTER94
GICDA_IROUTER95
GICDA_IROUTER96
GICDA_IROUTER97
GICDA_IROUTER98
GICDA_IROUTER99
GICDA_IROUTER100
GICDA_IROUTER101
GICDA_IROUTER102
GICDA_IROUTER103
GICDA_IROUTER104
GICDA_IROUTER105
GICDA_IROUTER106
GICDA_IROUTER107
GICDA_IROUTER108
GICDA_IROUTER109
GICDA_IROUTER110
GICDA_IROUTER111
GICDA_IROUTER112
GICDA_IROUTER113
GICDA_IROUTER114
GICDA_IROUTER115
GICDA_IROUTER116
GICDA_IROUTER117
GICDA_IROUTER118
GICDA_IROUTER119
GICDA_IROUTER120
GICDA_IROUTER121
GICDA_IROUTER122
GICDA_IROUTER123
GICDA_IROUTER124
GICDA_IROUTER125
GICDA_IROUTER126
GICDA_IROUTER127
GICDA_IROUTER128
GICDA_IROUTER129
GICDA_IROUTER130
GICDA_IROUTER131
GICDA_IROUTER132
GICDA_IROUTER133
GICDA_IROUTER134
GICDA_IROUTER135
GICDA_IROUTER136
GICDA_IROUTER137
GICDA_IROUTER138
GICDA_IROUTER139
GICDA_IROUTER140
GICDA_IROUTER141
GICDA_IROUTER142
GICDA_IROUTER143
GICDA_IROUTER144
GICDA_IROUTER145
GICDA_IROUTER146
GICDA_IROUTER147
GICDA_IROUTER148
GICDA_IROUTER149
GICDA_IROUTER150
GICDA_IROUTER151
GICDA_IROUTER152
GICDA_IROUTER153
GICDA_IROUTER154
GICDA_IROUTER155
GICDA_IROUTER156
GICDA_IROUTER157
GICDA_IROUTER158
GICDA_IROUTER159
GICDA_IROUTER160
GICDA_IROUTER161
GICDA_IROUTER162
GICDA_IROUTER163
GICDA_IROUTER164
GICDA_IROUTER165
GICDA_IROUTER166
GICDA_IROUTER167
GICDA_IROUTER168
GICDA_IROUTER169
GICDA_IROUTER170
GICDA_IROUTER171
GICDA_IROUTER172
GICDA_IROUTER173
GICDA_IROUTER174
GICDA_IROUTER175
GICDA_IROUTER176
GICDA_IROUTER177
GICDA_IROUTER178
GICDA_IROUTER179
GICDA_IROUTER180
GICDA_IROUTER181
GICDA_IROUTER182
GICDA_IROUTER183
GICDA_IROUTER184
GICDA_IROUTER185
GICDA_IROUTER186
GICDA_IROUTER187
GICDA_IROUTER188
GICDA_IROUTER189
GICDA_IROUTER190
GICDA_IROUTER191
GICDA_IROUTER192
GICDA_IROUTER193
GICDA_IROUTER194
GICDA_IROUTER195
GICDA_IROUTER196
GICDA_IROUTER197
GICDA_IROUTER198
GICDA_IROUTER199
GICDA_IROUTER200
GICDA_IROUTER201
GICDA_IROUTER202
GICDA_IROUTER203
GICDA_IROUTER204
GICDA_IROUTER205
GICDA_IROUTER206
GICDA_IROUTER207
GICDA_IROUTER208
GICDA_IROUTER209
GICDA_IROUTER210
GICDA_IROUTER211
GICDA_IROUTER212
GICDA_IROUTER213
GICDA_IROUTER214
GICDA_IROUTER215
GICDA_IROUTER216
GICDA_IROUTER217
GICDA_IROUTER218
GICDA_IROUTER219
GICDA_IROUTER220
GICDA_IROUTER221
GICDA_IROUTER222
GICDA_IROUTER223
GICDA_IROUTER224
GICDA_IROUTER225
GICDA_IROUTER226
GICDA_IROUTER227
GICDA_IROUTER228
GICDA_IROUTER229
GICDA_IROUTER230
GICDA_IROUTER231
GICDA_IROUTER232
GICDA_IROUTER233
GICDA_IROUTER234
GICDA_IROUTER235
GICDA_IROUTER236
GICDA_IROUTER237
GICDA_IROUTER238
GICDA_IROUTER239
GICDA_IROUTER240
GICDA_IROUTER241
GICDA_IROUTER242
GICDA_IROUTER243
GICDA_IROUTER244
GICDA_IROUTER245
GICDA_IROUTER246
GICDA_IROUTER247
GICDA_IROUTER248
GICDA_IROUTER249
GICDA_IROUTER250
GICDA_IROUTER251
GICDA_IROUTER252
GICDA_IROUTER253
GICDA_IROUTER254
GICDA_IROUTER255
GICDA_IROUTER256
GICDA_IROUTER257
GICDA_IROUTER258
GICDA_IROUTER259
GICDA_IROUTER260
GICDA_IROUTER261
GICDA_IROUTER262
GICDA_IROUTER263
GICDA_IROUTER264
GICDA_IROUTER265
GICDA_IROUTER266
GICDA_IROUTER267
GICDA_IROUTER268
GICDA_IROUTER269
GICDA_IROUTER270
GICDA_IROUTER271
GICDA_IROUTER272
GICDA_IROUTER273
GICDA_IROUTER274
GICDA_IROUTER275
GICDA_IROUTER276
GICDA_IROUTER277
GICDA_IROUTER278
GICDA_IROUTER279
GICDA_IROUTER280
GICDA_IROUTER281
GICDA_IROUTER282
GICDA_IROUTER283
GICDA_IROUTER284
GICDA_IROUTER285
GICDA_IROUTER286
GICDA_IROUTER287
GICDA_IROUTER288
GICDA_IROUTER289
GICDA_IROUTER290
GICDA_IROUTER291
GICDA_IROUTER292
GICDA_IROUTER293
GICDA_IROUTER294
GICDA_IROUTER295
GICDA_IROUTER296
GICDA_IROUTER297
GICDA_IROUTER298
GICDA_IROUTER299
GICDA_IROUTER300
GICDA_IROUTER301
GICDA_IROUTER302
GICDA_IROUTER303
GICDA_IROUTER304
GICDA_IROUTER305
GICDA_IROUTER306
GICDA_IROUTER307
GICDA_IROUTER308
GICDA_IROUTER309
GICDA_IROUTER310
GICDA_IROUTER311
GICDA_IROUTER312
GICDA_IROUTER313
GICDA_IROUTER314
GICDA_IROUTER315
GICDA_IROUTER316
GICDA_IROUTER317
GICDA_IROUTER318
GICDA_IROUTER319
GICDA_IROUTER320
GICDA_IROUTER321
GICDA_IROUTER322
GICDA_IROUTER323
GICDA_IROUTER324
GICDA_IROUTER325
GICDA_IROUTER326
GICDA_IROUTER327
GICDA_IROUTER328
GICDA_IROUTER329
GICDA_IROUTER330
GICDA_IROUTER331
GICDA_IROUTER332
GICDA_IROUTER333
GICDA_IROUTER334
GICDA_IROUTER335
GICDA_IROUTER336
GICDA_IROUTER337
GICDA_IROUTER338
GICDA_IROUTER339
GICDA_IROUTER340
GICDA_IROUTER341
GICDA_IROUTER342
GICDA_IROUTER343
GICDA_IROUTER344
GICDA_IROUTER345
GICDA_IROUTER346
GICDA_IROUTER347
GICDA_IROUTER348
GICDA_IROUTER349
GICDA_IROUTER350
GICDA_IROUTER351
GICDA_IROUTER352
GICDA_IROUTER353
GICDA_IROUTER354
GICDA_IROUTER355
GICDA_IROUTER356
GICDA_IROUTER357
GICDA_IROUTER358
GICDA_IROUTER359
GICDA_IROUTER360
GICDA_IROUTER361
GICDA_IROUTER362
GICDA_IROUTER363
GICDA_IROUTER364
GICDA_IROUTER365
GICDA_IROUTER366
GICDA_IROUTER367
GICDA_IROUTER368
GICDA_IROUTER369
GICDA_IROUTER370
GICDA_IROUTER371
GICDA_IROUTER372
GICDA_IROUTER373
GICDA_IROUTER374
GICDA_IROUTER375
GICDA_IROUTER376
GICDA_IROUTER377
GICDA_IROUTER378
GICDA_IROUTER379
GICDA_IROUTER380
GICDA_IROUTER381
GICDA_IROUTER382
GICDA_IROUTER383
GICDA_IROUTER384
GICDA_IROUTER385
GICDA_IROUTER386
GICDA_IROUTER387
GICDA_IROUTER388
GICDA_IROUTER389
GICDA_IROUTER390
GICDA_IROUTER391
GICDA_IROUTER392
GICDA_IROUTER393
GICDA_IROUTER394
GICDA_IROUTER395
GICDA_IROUTER396
GICDA_IROUTER397
GICDA_IROUTER398
GICDA_IROUTER399
GICDA_IROUTER400
GICDA_IROUTER401
GICDA_IROUTER402
GICDA_IROUTER403
GICDA_IROUTER404
GICDA_IROUTER405
GICDA_IROUTER406
GICDA_IROUTER407
GICDA_IROUTER408
GICDA_IROUTER409
GICDA_IROUTER410
GICDA_IROUTER411
GICDA_IROUTER412
GICDA_IROUTER413
GICDA_IROUTER414
GICDA_IROUTER415
GICDA_IROUTER416
GICDA_IROUTER417
GICDA_IROUTER418
GICDA_IROUTER419
GICDA_IROUTER420
GICDA_IROUTER421
GICDA_IROUTER422
GICDA_IROUTER423
GICDA_IROUTER424
GICDA_IROUTER425
GICDA_IROUTER426
GICDA_IROUTER427
GICDA_IROUTER428
GICDA_IROUTER429
GICDA_IROUTER430
GICDA_IROUTER431
GICDA_IROUTER432
GICDA_IROUTER433
GICDA_IROUTER434
GICDA_IROUTER435
GICDA_IROUTER436
GICDA_IROUTER437
GICDA_IROUTER438
GICDA_IROUTER439
GICDA_IROUTER440
GICDA_IROUTER441
GICDA_IROUTER442
GICDA_IROUTER443
GICDA_IROUTER444
GICDA_IROUTER445
GICDA_IROUTER446
GICDA_IROUTER447
GICDA_IROUTER448
GICDA_IROUTER449
GICDA_IROUTER450
GICDA_IROUTER451
GICDA_IROUTER452
GICDA_IROUTER453
GICDA_IROUTER454
GICDA_IROUTER455
GICDA_IROUTER456
GICDA_IROUTER457
GICDA_IROUTER458
GICDA_IROUTER459
GICDA_IROUTER460
GICDA_IROUTER461
GICDA_IROUTER462
GICDA_IROUTER463
GICDA_IROUTER464
GICDA_IROUTER465
GICDA_IROUTER466
GICDA_IROUTER467
GICDA_IROUTER468
GICDA_IROUTER469
GICDA_IROUTER470
GICDA_IROUTER471
GICDA_IROUTER472
GICDA_IROUTER473
GICDA_IROUTER474
GICDA_IROUTER475
GICDA_IROUTER476
GICDA_IROUTER477
GICDA_IROUTER478
GICDA_IROUTER479
GICDA_IROUTER480
GICDA_IROUTER481
GICDA_IROUTER482
GICDA_IROUTER483
GICDA_IROUTER484
GICDA_IROUTER485
GICDA_IROUTER486
GICDA_IROUTER487
GICDA_IROUTER488
GICDA_IROUTER489
GICDA_IROUTER490
GICDA_IROUTER491
GICDA_IROUTER492
GICDA_IROUTER493
GICDA_IROUTER494
GICDA_IROUTER495
GICDA_IROUTER496
GICDA_IROUTER497
GICDA_IROUTER498
GICDA_IROUTER499
GICDA_IROUTER500
GICDA_IROUTER501
GICDA_IROUTER502
GICDA_IROUTER503
GICDA_IROUTER504
GICDA_IROUTER505
GICDA_IROUTER506
GICDA_IROUTER507
GICDA_IROUTER508
GICDA_IROUTER509
GICDA_IROUTER510
GICDA_IROUTER511
GICDA_IROUTER512
GICDA_IROUTER513
GICDA_IROUTER514
GICDA_IROUTER515
GICDA_IROUTER516
GICDA_IROUTER517
GICDA_IROUTER518
GICDA_IROUTER519
GICDA_IROUTER520
GICDA_IROUTER521
GICDA_IROUTER522
GICDA_IROUTER523
GICDA_IROUTER524
GICDA_IROUTER525
GICDA_IROUTER526
GICDA_IROUTER527
GICDA_IROUTER528
GICDA_IROUTER529
GICDA_IROUTER530
GICDA_IROUTER531
GICDA_IROUTER532
GICDA_IROUTER533
GICDA_IROUTER534
GICDA_IROUTER535
GICDA_IROUTER536
GICDA_IROUTER537
GICDA_IROUTER538
GICDA_IROUTER539
GICDA_IROUTER540
GICDA_IROUTER541
GICDA_IROUTER542
GICDA_IROUTER543
GICDA_IROUTER544
GICDA_IROUTER545
GICDA_IROUTER546
GICDA_IROUTER547
GICDA_IROUTER548
GICDA_IROUTER549
GICDA_IROUTER550
GICDA_IROUTER551
GICDA_IROUTER552
GICDA_IROUTER553
GICDA_IROUTER554
GICDA_IROUTER555
GICDA_IROUTER556
GICDA_IROUTER557
GICDA_IROUTER558
GICDA_IROUTER559
GICDA_IROUTER560
GICDA_IROUTER561
GICDA_IROUTER562
GICDA_IROUTER563
GICDA_IROUTER564
GICDA_IROUTER565
GICDA_IROUTER566
GICDA_IROUTER567
GICDA_IROUTER568
GICDA_IROUTER569
GICDA_IROUTER570
GICDA_IROUTER571
GICDA_IROUTER572
GICDA_IROUTER573
GICDA_IROUTER574
GICDA_IROUTER575
GICDA_ICLAR2
GICDA_ICLAR3
GICDA_ICLAR4
GICDA_ICLAR5
GICDA_ICLAR6
GICDA_ICLAR7
GICDA_ICLAR8
GICDA_ICLAR9
GICDA_ICLAR10
GICDA_ICLAR11
GICDA_ICLAR12
GICDA_ICLAR13
GICDA_ICLAR14
GICDA_ICLAR15
GICDA_ICLAR16
GICDA_ICLAR17
GICDA_ICLAR18
GICDA_ICLAR19
GICDA_ICLAR20
GICDA_ICLAR21
GICDA_ICLAR22
GICDA_ICLAR23
GICDA_ICLAR24
GICDA_ICLAR25
GICDA_ICLAR26
GICDA_ICLAR27
GICDA_ICLAR28
GICDA_ICLAR29
GICDA_ICLAR30
GICDA_ICLAR31
GICDA_ICLAR32
GICDA_ICLAR33
GICDA_ICLAR34
GICDA_ICLAR35
GICDA_IERRR1
GICDA_IERRR2
GICDA_IERRR3
GICDA_IERRR4
GICDA_IERRR5
GICDA_IERRR6
GICDA_IERRR7
GICDA_IERRR8
GICDA_IERRR9
GICDA_IERRR10
GICDA_IERRR11
GICDA_IERRR12
GICDA_IERRR13
GICDA_IERRR14
GICDA_IERRR15
GICDA_IERRR16
GICDA_IERRR17
GICDA_CFGID
GICDA_PIDR4
GICDA_PIDR5
GICDA_PIDR6
GICDA_PIDR7
GICDA_PIDR0
GICDA_PIDR1
GICDA_PIDR2
GICDA_PIDR3
GICDA_CIDR0
GICDA_CIDR1
GICDA_CIDR2
GICDA_CIDR3
LWHPS2FPGA_memory Address Block Group
lwhps2fpga_4M Address Map
lwhps2fpga_512M Address Map
HPS2FPGA_memory Address Block Group
hps2fpga_1G Address Map
hps2fpga_15G Address Map
hps2fpga_240G Address Map
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