hdsktimeout

         The Warm Reset handshake time-out controls the amount of time to wait for the ETR, FPGA and SDRAM interface to respond to a reset handshake request. The register defaults to 10,240 l4_sys_free_clk cycles, which at 100 MHz will be 102.4 micro-seconds.  This value will be a 25 bit programmable value in SW.  The maximum programmable value would be 2^25-1 l4_sys_free_clk cycles.

Module Instance	Base Address	Register Address
`i_rst_mgr_rstmgr`	`0xFFD11000`	`0xFFD11064`

Size: 32

Offset: 0x64

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`val` `RW 0x2800`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`val` `RW 0x2800`

hdsktimeout Fields

Bit	Name	Description	Access	Reset
31:0	`val`	ETR, FPGA and SDRAM interface handshake time-out value.	`RW`	`0x2800`