ECC_REG2ARDDATABUS_BEAT0

         ECC Reg2aRddatabus_beat0
      
Module Instance Base Address Register Address
soc_hmc_adp_csr_inst_0_ocp_slv_block 0xF8011000 0xF8011170

Size: 32

Offset: 0x170

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ECC3BUS

0x0

ECC2BUS

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ECC1BUS

0x0

ECC0BUS

0x0

ECC_REG2ARDDATABUS_BEAT0 Fields

Bit Name Description Access Reset
31:24 ECC3BUS
Data ECC from the register will be written to the RAM
RW 0x0
23:16 ECC2BUS
Data ECC from the register will be written to the RAM
RW 0x0
15:8 ECC1BUS
Data ECC from the register will be written to the RAM
RW 0x0
7:0 ECC0BUS
Data ECC from the register will be written to the RAM
RW 0x0