WDT_TORR
Timeout Range Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_watchdog_0_wdt_address_block | 0xFFD00200 | 0xFFD00204 |
| i_watchdog_1_wdt_address_block | 0xFFD00300 | 0xFFD00304 |
| i_watchdog_2_wdt_address_block | 0xFFD00400 | 0xFFD00404 |
| i_watchdog_3_wdt_address_block | 0xFFD00500 | 0xFFD00504 |
Size: 32
Offset: 0x4
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
Reserved |
TOP_INIT RW 0xF |
TOP RW 0xF |
|||||||||||||
WDT_TORR Fields
| Bit | Name | Description | Access | Reset | ||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31:8 | Reserved |
Reserved and read as 0. |
RO | 0x0 | ||||||||||||||||||||||||||||||||||
| 7:4 | TOP_INIT |
Timeout period for initialization.
Writes to these register bits have no effect when the configuration
parameter WDT_HC_TOP = 1 or WDT_ALWAYS_EN = 1. Used to
select the timeout period that the watchdog counter restarts from for
the first counter restart (kick). This register should be written after
reset and before the WDT is enabled.
A change of the TOP_INIT is seen only once the WDT has been
enabled, and any change after the first kick is not seen as subsequent
kicks use the period specified by the TOP bits.
The range of values is limited by the WDT_CNT_WIDTH. If
TOP_INIT is programmed to select a range that is greater than the
counter width, the timeout period is truncated to fit to the counter
width. This affects only the non-user specified values as users are
limited to these boundaries during configuration.
The range of values available for a 32-bit watchdog counter are:
Where i = TOP_INIT and
t = timeout period
For i = 0 to 15
if WDT_USE_FIX_TOP==1
t = 2(16 + i)
else
t = WDT_USER_TOP_INIT_(i)
NOTE: These bits exist only when the configuration parameter
WDT_DUAL_TOP = 1, otherwise, they are fixed at zero.
|
RW | 0xF | ||||||||||||||||||||||||||||||||||
| 3:0 | TOP |
Timeout period. Writes have no effect when the configuration parameter
WDT_HC_TOP = 1, thus making this register read-only. This field is used
to select the timeout period from which the watchdog counter restarts.
A change of the timeout period takes effect only after the next counter
restart (kick). The range of values is limited by the WDT_CNT_WIDTH. If
TOP is programmed to select a range that is greater than the counter width,
the timeout period is truncated to fit to the counter width. This affects
only the non-user specified values as users are limited to these boundaries
during configuration. The range of values available for a 32-bit watchdog
counter are:
Where i = TOP and
t = timeout period
For i = 0 to 15
if WDT_USE_FIX_TOP==1
t = 2(16 + i)
else
t = WDT_USER_TOP_(i)
|
RW | 0xF |