noc_fw_l4_per_scr Summary

L4_PER Security Control Registers (SCR)

Base Address: 0xFFD21000

Register Address Offset	Bit Fields
`noc_fw_l4_per_l4_per_scr`
`nand_register` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`mpu` `RW 0x0`
`nand_data` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`mpu` `RW 0x0`
`usb0_register` `0xC` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`mpu` `RW 0x0`
`usb1_register` `0x10` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`mpu` `RW 0x0`
`spi_master0` `0x1C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`dma` `RW 0x0`	`Reserved`							`mpu` `RW 0x0`
`spi_master1` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`dma` `RW 0x0`	`Reserved`							`mpu` `RW 0x0`
`spi_slave0` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`dma` `RW 0x0`	`Reserved`							`mpu` `RW 0x0`
`spi_slave1` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`dma` `RW 0x0`	`Reserved`							`mpu` `RW 0x0`
`emac0` `0x2C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`mpu` `RW 0x0`
`emac1` `0x30` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`mpu` `RW 0x0`
`emac2` `0x34` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`mpu` `RW 0x0`
`sdmmc` `0x40` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`mpu` `RW 0x0`
`gpio0` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`dma` `RW 0x0`	`Reserved`							`mpu` `RW 0x0`
`gpio1` `0x48` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`dma` `RW 0x0`	`Reserved`							`mpu` `RW 0x0`
`i2c0` `0x50` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`dma` `RW 0x0`	`Reserved`							`mpu` `RW 0x0`
`i2c1` `0x54` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`dma` `RW 0x0`	`Reserved`							`mpu` `RW 0x0`
`i2c2` `0x58` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`dma` `RW 0x0`	`Reserved`							`mpu` `RW 0x0`
`i2c3` `0x5C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`dma` `RW 0x0`	`Reserved`							`mpu` `RW 0x0`
`i2c4` `0x60` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`dma` `RW 0x0`	`Reserved`							`mpu` `RW 0x0`
`sp_timer0` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`dma` `RW 0x0`	`Reserved`							`mpu` `RW 0x0`
`sp_timer1` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`dma` `RW 0x0`	`Reserved`							`mpu` `RW 0x0`
`uart0` `0x6C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`dma` `RW 0x0`	`Reserved`							`mpu` `RW 0x0`
`uart1` `0x70` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`axi_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`dma` `RW 0x0`	`Reserved`							`mpu` `RW 0x0`