ctrl

         Contains fields that control the entire Clock Manager.

Module Instance	Base Address	Register Address
`i_clk_mgr_clkmgr`	`0xFFD10000`	`0xFFD10000`

Size: 32

Offset: 0x0

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`						`swctrlbtclksel` `RW 0x0`	`swctrlbtclken` `RW 0x0`	`Reserved`							`bootmode` `RW 0x1`

ctrl Fields

Bit	Name	Description	Access	Reset
9	`swctrlbtclksel`	This bit is only used if swctrlbtclken is set. If 1, boot_clk source will be from cb_intosc_hs_clk divided by 2. If 0, boot_clk source will be from the external oscillator (EOSC1). This bit is cleared on a cold reset. Warm reset has no affect on this bit.	`RW`	`0x0`
8	`swctrlbtclken`	If set, then Software will take control of the boot_clk mux select. If set, then swctrlbtclksel will determine the mux setting. If not set, the security features will determine the fuse settings. This bit is cleared on a cold reset. Warm reset has no affect on this bit.	`RW`	`0x0`
0	`bootmode`	When set the Clock Manager is in Boot Mode. In Boot Mode Clock Manager register settings defining clock behavior are ignored and clocks are set to their Boot Mode settings. All clocks will be bypassed and external HW managed counters and dividers will be set to divide by 1. This bit should only be cleared when clocks have been correctly configured. This field is set on a cold reset and optionally on a warm reset. SW may set this bit to force the clocks into Boot Mode. SW exits Boot Mode by clearing this bit.	`RW`	`0x1`

Bit

Name

Description

Access

Reset

swctrlbtclksel

This bit is only used if swctrlbtclken is set.

If 1, boot_clk source will be from cb_intosc_hs_clk divided by 2.  If 0, boot_clk source will be from the external oscillator (EOSC1).

This bit is cleared on a cold reset. Warm reset has no affect on this bit.

RW

0x0

swctrlbtclken

If set, then Software will take control of the boot_clk mux select.  If set, then swctrlbtclksel will determine the mux setting.  If not set, the security features will determine the fuse settings.

This bit is cleared on a cold reset. Warm reset has no affect on this bit.

RW

0x0

bootmode

When set the Clock Manager is in Boot Mode.
In Boot Mode Clock Manager register settings defining clock behavior are ignored and clocks are set to their Boot Mode settings.  All clocks will be bypassed and external HW managed counters and dividers will be set to divide by 1.
This bit should only be cleared when clocks have been correctly configured. 
This field is set on a cold reset and optionally on a warm reset. SW may set this bit to force the clocks into Boot Mode.  SW exits Boot Mode by clearing this bit.

RW

0x1