reg_sbcfg1
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF8010060

Size: 32

Offset: 0x60

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_reserve9

RW 0x0

cfg_rfsh_post_lower_limit

RW 0x0

cfg_rfsh_post_upper_limit

RW 0x0

cfg_post_rfsh_en

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_rfsh_pre_upper_limit

RW 0x0

cfg_pre_rfsh_en

RW 0x0

cfg_t_param_arf_to_valid

RW 0x0

cfg_dual_ping_pong_en

RW 0x0

reg_sbcfg1 Fields

Bit Name Description Access Reset
31:27 cfg_reserve9 
iohmc_ctrl_mmr_top_inst.cfg_reserve9[4:0]
Name:Reserved
Description:TBD
   
26:22 cfg_rfsh_post_lower_limit 
iohmc_ctrl_mmr_top_inst.cfg_rfsh_post_lower_limit[4:0]
Name:Reserved
Description:TBD
   
21:17 cfg_rfsh_post_upper_limit 
iohmc_ctrl_mmr_top_inst.cfg_rfsh_post_upper_limit[4:0]
Name:Reserved
Description:TBD
   
16 cfg_post_rfsh_en 
iohmc_ctrl_mmr_top_inst.cfg_post_rfsh_en
Name:Reserved
Description:TBD
   
15:12 cfg_rfsh_pre_upper_limit 
iohmc_ctrl_mmr_top_inst.cfg_rfsh_pre_upper_limit[3:0]
Name:Reserved
Description:TBD
   
11 cfg_pre_rfsh_en 
iohmc_ctrl_mmr_top_inst.cfg_pre_rfsh_en
Name:Reserved
Description:TBD
   
10:1 cfg_t_param_arf_to_valid 
iohmc_ctrl_mmr_top_inst.cfg_t_param_arf_to_valid[9:0]
Name:Auto Refresh to Valid
Description:Auto Refresh to valid DRAM command window. When operating in DDR4 3DS mode, this register serves as the SLR (same logical rank) variant of tRFC.
   
0 cfg_dual_ping_pong_en 
iohmc_ctrl_mmr_top_inst.cfg_dual_ping_pong_en
Name:Reserved
Description:TBD