ECC_ERRGENADDR_5

         Error address register
      
Module Instance Base Address Register Address
soc_hmc_adp_csr_inst_0_ocp_slv_block 0xF8011000 0xF8011270

Size: 32

Offset: 0x270

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADDR

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDR

0x0

ECC_ERRGENADDR_5 Fields

Bit Name Description Access Reset
31:0 ADDR
For decoder 5.
Address generated with SER or address mismatch logic. Address will be driven by the ECC decoder on every read latched by the RAM independent of ECCDiagon is on.
RO 0x0