Intel_grp Address Map

Contains registers with settings for Altera internal use.

Module Instance	Base Address	End Address
`i_clk_mgr_alteragrp`	`0xFFD100D0`	`0xFFD100F7`

Register	Offset	Width	Access	Reset Value	Description
`jtag`	`0x0`	`32`	`RW`	`0x00000180`	Jtag control registers for the PLLs - Testing Access
`emacactr`	`0x4`	`32`	`RW`	`0x00000001`	Main PLL Control Register for emaca_free_clk
`emacbctr`	`0x8`	`32`	`RW`	`0x00010003`	MAin PLL Control Register for emacb_free_clk
`emacptpctr`	`0xC`	`32`	`RW`	`0x00010001`	Main PLL Control Register for emac_ptp_free_clk
`gpiodbctr`	`0x10`	`32`	`RW`	`0x00010000`	Peripheral PLL Control Register for gpio_db_free_clk
`sdmmcctr`	`0x14`	`32`	`RW`	`0x00010000`	Peripheral PLL Control Register for sdmmc_free_clk
`s2fuser0ctr`	`0x18`	`32`	`RW`	`0x00000000`	Control Register for s2f_user0_free_clk registers
`s2fuser1ctr`	`0x1C`	`32`	`RW`	`0x00000000`	Main PLL Control Register for s2f_user1_free_clk
`psirefctr`	`0x20`	`32`	`RW`	`0x00000000`	Main PLL Control Register for psi_ref_free_clk
`extcntrst`	`0x24`	`32`	`RW`	`0x000000FF`	Pingpong or External Counter reset control